[kernel] WITH_DEV_PCIE -> WITH_KERNEL_PCIE

Hard-code this in KERNEL_DEFINES rather than relying on the
magic predefine based on the presence of the dev/pcie module.

Test: CQ & manual verification that kernel text size didn't change
Change-Id: Id827a8a93bc61ac8b1d7727f51a18f53277a7a16

[kernel][platform] run clang-fmt on all of kernel/platform

Change-Id: I8dcc6ca434f0c77e4fa7c23c202772abf03e1f1d

[kernel][pci] add TOLUD table for another chipset

Seems there are earlier core chipsets in the 0x01xx DID range that have
valid TOLUD registers as well.

Change-Id: Iaa71956067bee2527e055f4fcc276e68963af937

[pci] Move quirks to extern tables

The previous method of using __WEAK references referring back
to a specific section was causing issues for kernel aslr
development. This moves quirks into a static table with a __WEAK
default empty table for platforms that don't have pci hardware
quirks to worry about.

Change-Id: I8e67df1148b6863362729f7d905fd7079b685827

[kernel][platform] Convert kernel/platform to use zx_status_t

Change-Id: If07f3ab0f67f7c3408fc520d48d9cde1b7d735be

[zx] Magenta -> Zircon

The Great Renaming is here!

Change-Id: I3229bdeb2a3d0e40fb4db6fec8ca7d971fbffb94

[zircon][mxtl->fbl] Rename mxtl to fbl

Change-Id: Ie21b6498e1bfb0a7fa0315e40b9e5c3ee78646be

[kernel][mxtl] Clean up some dependencies of mxtl::count_of

This adds both explicit includes of mxtl/algorithm.h, and module
dependencies.

Change-Id: I3b102a42df56c982b9c2c8913d8151c9c66198b6

[mxtl[[count_of] Prefer mxtl::count_of to countof in C++

Change-Id: I1fcbc61031df91542fc60d224b9c24e9b3b260cb

[pci] Add PIIX4 host controller to tolud table

Change-Id: Ic610eee5472ca8d876d2efb9458bb55593403774

[kernel][vm] objectify the mmu layer by adding a simple wrapper object

This just adds a wrapper object around the arch_mmu routines and
switches the high level api to an object oriented model. Subsequent
changes will remove the wrapper and have the two arches implement the
objects directly.

Change-Id: I5ce0d28db5612f4fbc9e0c87d2f6b22dcd09a3f1

[magenta][kernel][platform] Use the new MX_ERR_* and MX_OK names

Change-Id: I66e96d82886d10bc497eca0999be9a7e56ba7b16

[kernel][pci][amd] add a pcie quirk for AMD hardware to set the top of memory

AMD uses a known MSR to set the top of dram and thus mark where PCI
space starts. Read this at boot.

Change-Id: I1258fd8e7d6d48d003f8414d9851ca0ca518fa62

[pci] Add Kaby Lake DID to TOLUD quirk.

Note: I'm still waiting to hear back from Intel about whether or not
this DID is the proper one. Their docs say that it should be the same
as Skylake (0x19xx), but all of the hardware I have run into and seen
lspci dumps online seem to agree that the proper value for Kaby Lake
is 0x59xx.

MG-684 #done

Change-Id: I0ec00cc85d173effc04091d5e6bc8c4a3c484d66

[pci] PCI refactor for C++/PIO/MMIO

- Create PciConfig/PciMmioConfig/PciPioConfig classes for abstracting
out all PCI configuration reads/writes.
- Modify existing PCI codebase to not assume memory mapped MMIO address
space for all devices.
- Unify PCI device and bridge device types into a single entity
separated only by config register mappings.
- Update lspci command so it can properly show configuration data
whether a device is MMIO or PIO.
- Rework PCI Capabilities to use an object hierarchy and common
interface.
- Convert the remaining C interfaces in the PCI codebase to C++.
- Fix clang build.

Change-Id: Ia5b32f88f48ba317848befde853b9af9a489205d

[pcie][pc] Add a handler for the TOLUD quirk.

Recognize chipsets which have a Top-of-lower-usable-DRAM register and
subtract out the TOLUD region from the PCIe driver's allocatable MMIO
regions.

MG-325 #done

Change-Id: I5aadc19af008003f75c8f88e2e247b5e6587ad62