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321cb5ae |
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08-Sep-2018 |
Roland McGrath <mcgrathr@google.com> |
[kernel] Remove #if WITH_LIB_* conditionals There's only one configuration of the kernel per architecture, so these are always defined anyway. The global predefines based on what modules are in the dependency graph is not a feature future build systems will support. Test: CQ & manual verification that kernel text size didn't change Change-Id: Ib4c9b6c309c9ae4fc410701eef8fbdfad4d90641
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a0672e5d |
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02-May-2018 |
Roland McGrath <mcgrathr@google.com> |
[public][ulib][dev] Add __FALLTHROUGH macro for warning suppression GCC 7 enables -Wimplicit-fallthrough with -Wextra, so we'll get it. Clang has it available, so start using it and clean up code accordingly. The GCC feature will actually recognize some formulaic comments to suppress the warning. But there's also an explicit syntax, and C++17 added a standard one. So use that instead, via the new macro __FALLTHROUGH in <zircon/compiler.h>. TC-36 #comment Clean up code in preparation for more -Wimplicit-fallthrough Change-Id: I28309c91c32db1313d52f4255836c5ea687e141f
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8a15a973 |
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27-Mar-2018 |
Christopher Anderson <cja@google.com> |
[pci] Add 'k pciregions' command to dump address regions Change-Id: Ide663544363f25ac3cf500c04731c9efed135af5
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6ec289f0 |
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27-Oct-2017 |
Travis Geiselbrecht <travisg@google.com> |
[kernel][pcie] add NVMe to the class code table Change-Id: I8fb34453380b8b92a3b6ecf56517d1d9b9a96e94
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9a709d3b |
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26-Sep-2017 |
George Kulakowski <kulakowski@google.com> |
[kernel][pcie][status] Use zx_status_t Change-Id: I358be7e0a47a235ad489d1cfa52fde2606204df3
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f3e2126c |
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12-Sep-2017 |
Roland McGrath <mcgrathr@google.com> |
[zx] Magenta -> Zircon The Great Renaming is here! Change-Id: I3229bdeb2a3d0e40fb4db6fec8ca7d971fbffb94
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59e644b1 |
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07-Sep-2017 |
George Kulakowski <kulakowski@google.com> |
[zircon][mxtl->fbl] Rename mxtl to fbl Change-Id: Ie21b6498e1bfb0a7fa0315e40b9e5c3ee78646be
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c58222d2 |
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14-Aug-2017 |
George Kulakowski <kulakowski@google.com> |
[kernel][mxtl] Clean up some dependencies of mxtl::count_of This adds both explicit includes of mxtl/algorithm.h, and module dependencies. Change-Id: I3b102a42df56c982b9c2c8913d8151c9c66198b6
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e45d6f4b |
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11-Aug-2017 |
George Kulakowski <kulakowski@google.com> |
[mxtl[[count_of] Prefer mxtl::count_of to countof in C++ Change-Id: I1fcbc61031df91542fc60d224b9c24e9b3b260cb
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052e284a |
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03-Aug-2017 |
Dave Bort <dbort@google.com> |
[kernel] Make kernel always use mxtl:: for Mutex/AutoLock No functional changes, just makes everything more consistent. Change-Id: I9bba8630e79d6d9f1c1bdacc595cdbfc97cf75ba
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4d04624b |
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28-Jun-2017 |
Christopher Anderson <cja@google.com> |
[pci] Add DumpConfig to PciConfig Change-Id: I64bd5a8fc02ed5dd318050c5062e8c7dfa4e3138
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545e2143 |
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12-Jul-2017 |
Christopher Anderson <cja@google.com> |
[pci] Rework VMO resource handling - Fix bug where BARs that did not have allocations already resulted in VMOs having a base of 0x0 (MG-863) - Move VMO creation to the syscall layer rather than during device probing. This allows device bars and config to be a 1 vmo : 1 dispatcher : 1 process mapping and no longer results in object usage that is a grey area in our design (unblocks MG-826) - Add names to VMOs created by the pci bus driver. - With VMOs now being on demand all driver resources have been moved to handles (MG-641) These changes also make the transition to userspace simpler by removing resource creation from pcie_device. Change-Id: I4d15daf4af301bcf095ac0a7a18f954d3c8af024
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47c02055 |
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22-Jun-2017 |
Christopher Anderson <cja@google.com> |
[pci] Remove device claiming. Now that the device coordinator provides a central method for handing devices to drivers there is no longer a need to explicitly claim a device exclusively. This has the added benefit of simplifying the work that needs to be done when a driver is killed or unloaded. Change-Id: I5d0b810464ee0858430a08821b233e08a3b7abe6
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1903af67 |
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15-Jun-2017 |
George Kulakowski <kulakowski@google.com> |
[kernel][dev] Use the new MX_OK and MX_ERR_* names Change-Id: I8a280c31fdaedf7476c02f3b5ea8d0b473bf7979
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fb972adf |
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01-Mar-2017 |
Christopher Anderson <cja@google.com> |
[pci] Shift to using mx_pci_resource_t for memory PCI syscalls and protocols have been added to get pci_resource_t objects that encapsulate MMIO and PIO resources (Configs and BARs). In the MMIO case this means we're passing VMOs from the bus driver to users of the protocol. PIO is platform defined, but on x86 corresponds to an addr / size range. Change-Id: Ibcbd695efe3900316949adb837ee3c6a690c5802
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3f5a0f5b |
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03-Mar-2017 |
Travis Geiselbrecht <travisg@google.com> |
[kernel][debug] add additional flag to kernel console commands to signal panic time or not This will let us write debugging commands that dont acquire locks or behave differently if the system is crashed. Change-Id: I3befbd3454dac204e858f4e7a9307d88ab90478a
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5077b76a |
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05-Jan-2017 |
Christopher Anderson <cja@google.com> |
[pci] PCI refactor for C++/PIO/MMIO - Create PciConfig/PciMmioConfig/PciPioConfig classes for abstracting out all PCI configuration reads/writes. - Modify existing PCI codebase to not assume memory mapped MMIO address space for all devices. - Unify PCI device and bridge device types into a single entity separated only by config register mappings. - Update lspci command so it can properly show configuration data whether a device is MMIO or PIO. - Rework PCI Capabilities to use an object hierarchy and common interface. - Convert the remaining C interfaces in the PCI codebase to C++. - Fix clang build. Change-Id: Ia5b32f88f48ba317848befde853b9af9a489205d
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a2a90e3c |
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22-Nov-2016 |
John Grossman <johngro@google.com> |
[pcie] Allow multiple roots. Get rid of the root_complex_ singleton. Finish the AddRoot method and allow roots which manage buses other than zero. Redo the driver startup sequence so that all platform provided resources get added, then the driver gets explicitly started. Platform resources may no longer be changed after the initial startup has taken place. Next steps; move legacy IRQ swizzling behavior so that it is no longer a property of the platform, but is instead a property of roots added to the driver, as each root may have its own swizzle behavior as the legacy IRQ traverses it. MG-54 #done Change-Id: I65c4b9154bf34ac87cc8e190f8ffa5e05b5f4313
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de930efa |
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11-Nov-2016 |
Roland McGrath <mcgrathr@google.com> |
[kernel][dev][pcie] Drop useless cast in dump_pcie_raw_config parameter The source value and the destination parameter are both paddr_t. Casting to uint64_t in between is useless. Change-Id: Icde48b519553cd74fa643852010d3f3c22395cfa
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78c4f1ce |
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01-Nov-2016 |
John Grossman <johngro@google.com> |
[pcie] Tighten access on some of the PcieBusDriver methods. Create a class for the debug console command so it can be the bus driver's friend and have access to internal methods. Make some of the public methods of the bus driver private, as they should be. Revoke bus driver friendship from the device and bridge classes. Change-Id: I55610425cce5716b538e7a2ea9c369f030d6d45b
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3b4d5f55 |
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27-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie][c++] Continue conversion to C++ This time, turn pcie_(device|bridge)_state_t into Pcie(Device|Bridge). The process of turning these structs into proper C++ classes is not quite complete yet, but it is close. There are some surface area issues (exposing too much internal state) which still needs to be cleaned up. The areas where some further cleanup is needed include... 1) Capability parsing. 2) Refactoring code so that PCI device tree roots are not modeled as PcieBridges. 3) Legacy IRQ pin swizzling and handling. 4) Debug console code. 5) MMIO/PIO window allocation. 6) Bus topology locking (hot plug/unplug) Still, the major objects in the system are mostly well behaved classes now. This code should be landed soon in order to allow concurrent development without having a huge style refactor looming over everyone. Change-Id: Ib880c9690f2554aaf23823c1ccf891fead03b71b
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544684b9 |
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26-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie] Rip out kernel mode pcie drivers. Get rid of the concept of kernel mode pcie drivers. Start to lay the groundwork for re-defining the concept of "claimed" in order to allow user mode code to hold multiple references to a PCI device, at most one of which may have the device claimed at any point in time. Change-Id: I7596de831f40feca6f846c5f78d5f9283a673abc
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9ce2ea2c |
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21-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie] Continue init refactor. Continue to break initialization steps into smaller, separated tasks. Specifically... ++ Platform support (mostly support for legacy and MSI IRQs) is now provided via a platform implementation of an interface class which *must* be supplied at driver startup time. ++ ECAM regions (memory mapped config space) may be supplied independently via successive calls to the bus driver's AddEcamRegion method. ++ Start() has been replaced by AddRoot(uint bus_id). Currently, this does exactly the same thing that Start did (only one root is allowed, and it must be bus id #0), but it is moving in the direction of an interface which will allow us to add multiple roots when the internal implementation is ready for it. Change-Id: I4bdc344a9ea7493252970dae4bbe1a1b6a036435
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1232df97 |
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17-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie][c++] Continue PCIe bus driver migration to C++ ++ Turn the core driver state into a proper class. ++ Bring up the core driver state earlier in platform init. ++ Turn almost all of the mutex/spinlocks in the system into their C++ Mutex/SpinLock auto-initializing wrapper equivalents. ++ Convert almost entirely to using AutoLock/AutoSpinLocks and get rid of most of the "goto finished" instances in the system. MG-311 #comment Progress, converted bus driver into a class. Eliminated many gotos Change-Id: I6d3a116e7bbcfdd16127d13e344a24d86dddfe7d
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c6f7a2f2 |
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05-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie] Preserve BIOS BAR configuration when possible. Attempt to preserve a BIOS or bootloader supplied bootloader configuration when possible. Note: ++ Bridge configuration needs to be supplied by the BIOS and compatible with the available IO ranges supplied by ACPI. If they are not, the bridge and all downstream devices will be disabled (for now). See MG-324 ++ Devices which have been fully configured by BIOS, and which have configurations which can be preserved (no conflicts) will have their command register left alone until user mode device drivers have a chance to claim the device. This is to allow early-init code to keep using the device IO ranges, even though they have not formally claimed the device via the PCI framework. As soon as the device is claimed by a user mode driver, however, its windows will be closed. At this point, it is the driver's job to manage the handoff between any early-init system. If the driver fails to take control of the device, the device will be functionally disabled. ++ If a bootloader supplied configuration is unsatisfiable, the bus driver will attempt to dynamically allocate IO windows, but the windows will be immediately closed and not re-opened until a device driver takes control. ++ If a device's configuration cannot be satisfied, either statically or dynamically, it will be put into a "disabled" state. The device will still enumerate, allowing user mode code to know the device exists and to inspect its config space, but no resources (IO windows or IRQs) will be available for the device. MG-55 #done MG-57 #done MG-269 #done MG-320 #done Change-Id: I45a8703a0393e4e7bc0538afa1a89598e7c0aab8
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d48a7a11 |
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04-Oct-2016 |
John Grossman <johngro@google.com> |
[pcie][c++] Make progress on conversion to C++ ++ Make pcie_bridge_state_t derive from pcie_device_state_t ++ Convert almost all malloc/calloc/frees to new/delete ++ Convert most dynamically allocated raw pointers to managed pointers MG-311 #comment Conversion to managed pointers mostly complete. Change-Id: If1a88ad8a64c4cc481dbb0f6d60df1af538dc831
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93e42fdd |
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29-Sep-2016 |
John Grossman <johngro@google.com> |
[pcie] Convert PCIe bus driver to "C++" Note: this does not actually convert the driver to full on C++, it just switches to building with the C++ compiler and deals with some of the annoying differences between C++ and C compiler. In the short term, this will give the PCIe bus to ability to use other library code which is written in C++. In the longer term, other parts of the driver can be converted (as appropriate) to take advantage of some of the nicer safety oriented things which can be done with C++'s stronger stance on type safety. MG-311 #comment Initial conversion started. Code compiles with g++ Change-Id: If7c9fe98734ddfd64d587a6f73bc2ea6a515f6db
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