[kernel][pmm] first pass overhaul of the PMM

-Add a new PmmNode class that represents a pmm for a single NUMA node.
-Move main free queues into PmmNode.
-Make PmmArena be a child of PmmNode.
-Refactor the vm_page structure a bit to change how queues work. Make
the main queue node be intrinsic to the page, instead of per state.
-Move some per page helper routines into the page struct.
-Remove the KMAP flags, since they're not used on 64bit machines.

TODO:
-Make use of the LO_MEM flag for <4GB allocations
-Make use of the new active/inactive/wired queues in PmmNode
-Add support for multiple nodes in a NUMA system
-Keep page state count in PmmNode class to make page state counting less
expensive

Change-Id: I0ca5e55aad0bb2f393d2dc590b02f160e4740398

[iommu][intel] Beginnings of implementation

This provides a basic implementation of VT-d. It has the following
known limitations:

- No support for first level translation or requests-with-PASID
- Only supports 48-bit second level address spaces
- Currently performs identity-mapping only (i.e. acts more as a MPU
rather than an MMU)
- Performs synchronous IOTLB invalidations rather than using the
queued-invalidation feature.
- Does not support handing off across mexec

ZX-693 #comment

Change-Id: I6b2a7e49c5064065c2b6d06787bbd467fd666119