[arm64][hypervisor] Save and restore GIC APR register

The APR register controls the active priority of interrupt controller,
and should not be inconsistent with the state of the GIC. Prior to this
patch it was possible for the value of the APR from a previously
terminated guest (or theoretically another guest running in parallel on
the same CPU) to leak over to another guest. If the previous guest
terminated while APR was set to 1, then priority 0 interrupts would be
considered spurious and the guest would get stuck in a loop.

TEST=Ran guest_integration_tests on vim2. Ran zircon_guest on qemu to
test GICv3.

Change-Id: Iabf439eadb1a3c4a703b51590c29a2a9d6e35755

[arm64][GIC][hypervisor] Provide access to GICH MISR register

This register indicates active maintenance interrupt conditions. Access to
this register is not necessary to use underflow maintanece interrupt, but
it's interesting to see how often does VM exit happen because of underflow
interrupt and that is where access to this register comes in handy.

PD-105

Change-Id: I8cf63437546276585cda87240b9a4563711fbe15

[arm64][hypervisor] Remove ELRSR and VTR write

We should not be able to write these GIC registers, and we never call
the write functions, so remove the related code.

Also rename ELRS to ELRSR, as it is referred to in the manual.

Change-Id: I69819106993d80a4a97ea1cb04c95b2bbff04317

[arm64][hypervisor][gicv3] Correctly set VMCR

For GICv3, ICH_VMCR_EL2.VENG1 and ICH_VMCR_EL2.VPMR must be set,
otherwise interrupts will be ignored.

Additionally for GICv3, set the equivalent values to be pedantic.

ZX-2075 #done

Change-Id: I718bc064367d33182c732b95d6b0bfe613770ddc

[arm64][hypervisor][gicv3] Fix EL2 write_sysreg

The wrong register was being used when writing GICv3 system registers.

This also optimises the GIC register access, reducing the number of read
and writes needed, and therefore the number of transitions back and
forth from EL1 and EL2 when handling GICv3 system registers.

ZX-2075 #comment

Change-Id: If9e3b770071d51488adce6542b93267f35c91380

[gicV3] GICv3 virtualization support, to allow zircon-guest to run on QEMU

PD-50 #Done

Change-Id: I60a6937ad9a0515d1d737fbe562be517eb9a66ef

[arm64][hypervisor] Small GIC cleanup

These are some cleanups from a forthcoming CL.

Change-Id: Ide49fc77d6782f814b0f77680560186f69c41160

[kernel][gic] GIC code refactoring to add support for GICv3 in Hypervisor

Change-Id: Ia3e96db67ca507a26fbf537d8eb004c1d5a9b6b0