[arm64][hypervisor] Setup VTCR_EL2.

This configures VTCR_EL2 to accept the same page tables as user-space.

Change-Id: I3a78d3bdcc59744886051f93e8064420b711658e

[arm64][hypervisor] Setup initial VCPU state.

Before we can begin execution, we still need to setup VPIDR, VTCR, and
VTTBR. That will come in a follow up CL.

Change-Id: I307bc6c2ae3ca8af747afcd36d2616ea8e7419fd

[zircon][hypervisor] Fix SCR_EL3.HCE offset and set SCR_EL3.NS flag

According to the ARM Architecture Reference Manual (ARMv8) correct bit
for SCR_EL3.HCE is 8 and not 1. Also EL2 is only available in non-secure
work, so we need to set SCR_EL3.NS too.

Note that I currently don't have an equipment to test it on a real
hardware, so it's purely documentation based fix.

Change-Id: I629ad6765f670e5ae8552a91b467258f288f77f5

[arm64][hypervisor] Add El2CpuState.

Add code to manage EL2 CPU state. Currently this does the very minimum
and sets the EL2 stack for each CPU.

Next, I'll start setting up more of the EL2 state and also guest
physical address space.

Change-Id: I18b7f9d00b236e52cdc317dffe3b42fcffbcb8fe

[arm64] Remove arm64_el3_to_el1.

arm64_elX_to_el1 is already called from arm_reset in start.S before
lk_main is invoked, and neither the hikey960 or qemu seem to require
arm64_el3_to_el1.

This also removes some duplication between the two functions, for
example with hypervisor setup.

Change-Id: If94ce0e298e52ca39bed1a4a0b5a06f2e3eab5c6

[arm64][hypervisor] Enable HVC instruction.

HVC allows us to make hypervisor calls from EL1 to EL2.

Change-Id: Ie56b4ea5d963998ed475c4821ef4e1a443c39e1d

[arm64][efi] Support reloc/boot from efi

Change-Id: I40de15f4cdcda4878aa6b4af2b6b03daaebf1a60

[kernel] Add comments about the context_switch_frame structs

Add a comment to connect the function x86_64_context_switch() to
struct x86_64_context_switch_frame.

Otherwise, it's not obvious that arch_thread_initialize() populates a
data structure that x86_64_context_switch() later uses.

Do the same for the arm64 equivalents.

Change-Id: Ib58701e131376a24568ca268aae6f72dff8463fb

[kernel][arm] Add .cfi directives to assembly

MG-870 #comment arm portion

Change-Id: I5d64df47f282f52a29382bbac52779a74d5b3a7b

[kernel][arm64] Create a per cpu structure and use the x18 register to point to it

At the moment use it to store the oft-used current cpu number and
is-in-interrupt flag.

Change-Id: I3203358ca47a3b193ef7cb01356b67b50c74ff0f

[kernel][asm] Replace END with END_FUNCTION/END_DATA

MG-870 #comment baby steps

Change-Id: I1f1c2698c58612926e2fcfab8cfaed95833b7497

[kernel] remove the WITH_SMP flag

Always build the kernel with full SMP support.

Change-Id: I105f8e4127a93113c795ae80e1dc4d4b0d43abe8

[kernel][arm64] Add adr_global macro, use it

The new macro encapsulates the standard ADRP, ADD sequence for
materializing the address of a global symbol into a register.

Also change uses of a literal pool to materialize a normal address to
use adr_global. The remaining uses of load from literal pool should
be confined to the cases that need to load an unadjusted compile-time
constant rather than computing from the runtime PC.

Change-Id: I368b5544e008bfd0e10d3900184ccb7091031e98

[kernel][arm64] Build ARM64 kernel with -fsanitize=safe-stack

Change-Id: I953e5e19bf319e2047a467e64e3222808c07f9e3

[arm64][mp] Dynamically allocate initial stacks for mp

Change-Id: I7629e3b007677bec51fff6f7699a2c95e8d4f171

[kernel][arm64] clean up some assembly a bit

Add size markings to some functions.
Remove an extraneous align in start.S that was wasting
some amount of memory.

Change-Id: I21b35f4fd51422518828c2df49b2368514d84750

[aarc64] Pad context frame to prevent sp misalignment

context frame size should be a multiple of the sp alignment requirement
of 16 bytes, otherwise modifying the sp by the frame size can result
in misaligned stack pointers.

Change-Id: I644b8c75ad0672343177f24fb7911b74879d2045

[aarch64] Processor startup changes for cache sync and exception levels

Change-Id: Ibd408394c5727dabbd7abf1f8af31f8dc2a9205e

[magenta] Initial commit