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18051cc6 |
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20-Jun-2024 |
Mitchell Horne <mhorne@FreeBSD.org> |
riscv: drop l1pt argument from pmap_bootstrap() And from struct riscv_bootparams. It is no longer needed. Reviewed by: br, markj MFC after: 1 month Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D45470
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03b330e1 |
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05-Jun-2024 |
Ruslan Bukin <br@FreeBSD.org> |
riscv: add stage 2 translation to pmap. Add basic stage 2 translation support (guest-physical to host-physical). RISC-V hypervisor spec[1] introduces new translation schemes: Sv32x4, Sv39x4, Sv48x4 and Sv57x4. In each case, the size of the incoming address is widened by 2 bits (e.g. Sv39 becomes 41-bit system). To accommodate the 2 extra bits, the root page table (only) is expanded by a factor of four to be 16 KiB instead of the usual 4 KiB. The rest of page table system (including PTE format) is similar. This gives us 4x of memory space in each scheme, but it does not make sense to support all that memory for now. Allocate required amount of pages for the top directory in case of stage 2, but leave it unused. 1. https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc Reviewed by: mhorne Sponsored by: UKRI Differential Revision: https://reviews.freebsd.org/D45481
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b5e17840 |
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24-May-2024 |
Mitchell Horne <mhorne@FreeBSD.org> |
arm64, riscv: removed unused struct pv_addr No functional change. Reviewed by: markj MFC after: 3 days Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D45322
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95ee2897 |
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16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Remove $FreeBSD$: two-line .h pattern Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
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4961faaa |
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04-May-2023 |
John Baldwin <jhb@FreeBSD.org> |
pmap_{un}map_io_transient: Use bool instead of boolean_t. Reviewed by: imp, kib Differential Revision: https://reviews.freebsd.org/D39920
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1e0e335b |
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13-Apr-2023 |
Konstantin Belousov <kib@FreeBSD.org> |
amd64: fix PKRU and swapout interaction When vm_map_remove() is called from vm_swapout_map_deactivate_pages() due to swapout, PKRU attributes for the removed range must be kept intact. Provide a variant of pmap_remove(), pmap_map_delete(), to allow pmap to distinguish between real removes of the UVA mappings and any other internal removes, e.g. swapout. For non-amd64, pmap_map_delete() is stubbed by define to pmap_remove(). Reported by: andrew Reviewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D39556
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4d90a5af |
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07-Oct-2022 |
John Baldwin <jhb@FreeBSD.org> |
sys: Consolidate common implementation details of PV entries. Add a <sys/_pv_entry.h> intended for use in <machine/pmap.h> to define struct pv_entry, pv_chunk, and related macros and inline functions. Note that powerpc does not yet use this as while the mmu_radix pmap in powerpc uses the new scheme (albeit with fewer PV entries in a chunk than normal due to an used pv_pmap field in struct pv_entry), the Book-E pmaps for powerpc use the older style PV entries without chunks (and thus require the pv_pmap field). Suggested by: kib Reviewed by: kib Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D36685
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7ae99f80 |
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22-Sep-2022 |
John Baldwin <jhb@FreeBSD.org> |
pmap_unmapdev/bios: Accept a pointer instead of a vm_offset_t. This matches the return type of pmap_mapdev/bios. Reviewed by: kib, markj Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D36548
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e6639073 |
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23-Aug-2022 |
John Baldwin <jhb@FreeBSD.org> |
Define _NPCM and the last PC_FREEn constant in terms of _NPCPV. This applies one of the changes from 5567d6b4419b02a2099527228b1a51cc55a5b47d to other architectures besides arm64. Reviewed by: kib Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D36263
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ea8f128c |
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28-Jul-2022 |
John Baldwin <jhb@FreeBSD.org> |
pmap_mapdev: Consistently use vm_paddr_t for the first argument. The devmap variants used vm_offset_t for some reason, and a few places explicitly cast bus addresses to vm_offset_t. (Probably those casts along with similar casts for vm_size_t should just be removed and instead permit the compiler to DTRT.) Reviewed by: markj Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D35961
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828ea49d |
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28-Jul-2022 |
Mark Johnston <markj@FreeBSD.org> |
riscv: Avoid passing invalid addresses to pmap_fault() After the addition of SV48 support, VIRT_IS_VALID() did not exclude addresses that are in the SV39 address space hole but not in the SV48 address space hole. This can result in mishandling of accesses to that range when in SV39 mode. Fix the problem by modifying VIRT_IS_VALID() to use the runtime address space bounds. Then, if the address is invalid, and pcb_onfault is set, give vm_fault_trap() a chance to veto the access instead of panicking. PR: 265439 Reviewed by: jhb Reported and tested by: Robert Morris <rtm@lcs.mit.edu> Fixes: 31218f3209ac ("riscv: Add support for enabling SV48 mode") MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D35952
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59f192c5 |
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01-Mar-2022 |
Mark Johnston <markj@FreeBSD.org> |
riscv: Add various pmap definitions needed to support SV48 mode No functional change intended. Reviewed by: jhb MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34272
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82f4e0d0 |
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01-Mar-2022 |
Mark Johnston <markj@FreeBSD.org> |
riscv: Rename struct pmap's pm_l1 field to pm_top In SV48 mode, the top-level page will be an L0 page rather than an L1 page. Rename the field accordingly. No functional change intended. Reviewed by: alc, jhb MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34270
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682c00a6 |
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17-Oct-2021 |
Jessica Clarke <jrtc27@FreeBSD.org> |
riscv: Implement pmap_mapdev_attr This is needed for LinuxKPI's _ioremap_attr. This reuses the generic implementation introduced for aarch64, and itself requires implementing pmap_kenter, which is trivial to do given riscv currently treats all mapping attributes the same due to the Svpbmt extension not yet being ratified and in hardware. Reviewed by: markj, mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D32445
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1be2e16d |
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03-Oct-2021 |
Jessica Clarke <jrtc27@FreeBSD.org> |
riscv: Add a stub pmap_change_attr implementation pmap_change_attr is required by drm-kmod so we need the function to exist. Since the Svpbmt extension is on the horizon we will likely end up with a real implementation of it, so this stub implementation does all the necessary page table walking to validate the input, ensuring that no new errors are returned once it's implemented fully (other than due to out of memory conditions when demoting L2 entries) and providing a skeleton for that future implementation. Reviewed by: markj MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D31996
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041b7317 |
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10-Jul-2021 |
Konstantin Belousov <kib@FreeBSD.org> |
Add pmap_vm_page_alloc_check() which is the place to put MD asserts about allocated pages. On amd64, verify that allocated page does not belong to the kernel (text, data) or early allocated pages. Reviewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D31121
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317113bb |
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06-Jun-2021 |
Mark Johnston <markj@FreeBSD.org> |
riscv: Rename pmap_fault_fixup() to pmap_fault() This is consistent with other platforms, specifically arm and arm64. No functional change intended. Reviewed by: jrtc27 MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D30645
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5cff1f4d |
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10-Dec-2019 |
Mark Johnston <markj@FreeBSD.org> |
Introduce vm_page_astate. This is a 32-bit structure embedded in each vm_page, consisting mostly of page queue state. The use of a structure makes it easy to store a snapshot of a page's queue state in a stack variable and use cmpset loops to update that state without requiring the page lock. This change merely adds the structure and updates references to atomic state fields. No functional change intended. Reviewed by: alc, jeff, kib Sponsored by: Netflix, Intel Differential Revision: https://reviews.freebsd.org/D22650
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d4586dd3 |
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27-Sep-2019 |
Mark Johnston <markj@FreeBSD.org> |
Implement pmap_page_is_mapped() correctly on arm64 and riscv. We must also check for large mappings. pmap_page_is_mapped() is mostly used in assertions, so the problem was not very noticeable. Reviewed by: alc MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21824
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21943937 |
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15-Aug-2019 |
Jeff Roberson <jeff@FreeBSD.org> |
Move phys_avail definition into MI code. It is consumed in the MI layer and doing so adds more flexibility with less redundant code. Reviewed by: jhb, markj, kib Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D21250
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e7a9df16 |
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20-Feb-2019 |
Konstantin Belousov <kib@FreeBSD.org> |
Add kernel support for Intel userspace protection keys feature on Skylake Xeons. See SDM rev. 68 Vol 3 4.6.2 Protection Keys and the description of the RDPKRU and WRPKRU instructions. Reviewed by: markj Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D18893
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35c91b0c |
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13-Feb-2019 |
Mark Johnston <markj@FreeBSD.org> |
Implement per-CPU pmap activation tracking for RISC-V. This reduces the overhead of TLB invalidations by ensuring that we only interrupt CPUs which are using the given pmap. Tracking is performed in pmap_activate(), which gets called during context switches: from cpu_throw(), if a thread is exiting or an AP is starting, or cpu_switch() for a regular context switch. For now, pmap_sync_icache() still must interrupt all CPUs. Reviewed by: kib (earlier version), jhb Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D18874
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f6893f09 |
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13-Feb-2019 |
Mark Johnston <markj@FreeBSD.org> |
Implement transparent 2MB superpage promotion for RISC-V. This includes support for pmap_enter(..., psind=1) as described in the commit log message for r321378. The changes are largely modelled after amd64. arm64 has more stringent requirements around superpage creation to avoid the possibility of TLB conflict aborts, and these requirements do not apply to RISC-V, which like amd64 permits simultaneous caching of 4KB and 2MB translations for a given page. RISC-V's PTE format includes only two software bits, and as these are already consumed we do not have an analogue for amd64's PG_PROMOTED. Instead, pmap_remove_l2() always invalidates the entire 2MB address range. pmap_ts_referenced() is modified to clear PTE_A, now that we support both hardware- and software-managed reference and dirty bits. Also fix pmap_fault_fixup() so that it does not set PTE_A or PTE_D on kernel mappings. Reviewed by: kib (earlier version) Discussed with: jhb Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D18863 Differential Revision: https://reviews.freebsd.org/D18864 Differential Revision: https://reviews.freebsd.org/D18865 Differential Revision: https://reviews.freebsd.org/D18866 Differential Revision: https://reviews.freebsd.org/D18867 Differential Revision: https://reviews.freebsd.org/D18868
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b977d819 |
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18-Oct-2018 |
Ruslan Bukin <br@FreeBSD.org> |
Support RISC-V implementations that do not manage the A and D bits (e.g. RocketChip, lowRISC and derivatives). RISC-V page table entries support A (accessed) and D (dirty) bits. The spec makes hardware support for these bits optional. Implementations that do not manage these bits in hardware raise page faults for accesses to a valid page without A set and writes to a writable page without D set. Check for these types of faults when handling a page fault and fixup the PTE without calling vm_fault if they occur. Reviewed by: jhb, markj Approved by: re (gjb) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D17424
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3c8efd61 |
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18-Oct-2018 |
Ruslan Bukin <br@FreeBSD.org> |
Revert r339421 due to unintended files included to commit. Reported by: ian Approved by: re (gjb) Sponsored by: DARPA, AFRL
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53c6ad1d |
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18-Oct-2018 |
Ruslan Bukin <br@FreeBSD.org> |
Support RISC-V implementations that do not manage the A and D bits (e.g. RocketChip, lowRISC and derivatives). RISC-V page table entries support A (accessed) and D (dirty) bits. The spec makes hardware support for these bits optional. Implementations that do not manage these bits in hardware raise page faults for accesses to a valid page without A set and writes to a writable page without D set. Check for these types of faults when handling a page fault and fixup the PTE without calling vm_fault if they occur. Reviewed by: jhb, markj Approved by: re (gjb) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D17424
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9af94226 |
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26-Apr-2016 |
Ruslan Bukin <br@FreeBSD.org> |
Rework the list of all pmaps: embed the list link into pmap.
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02a37128 |
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25-Apr-2016 |
Ruslan Bukin <br@FreeBSD.org> |
o Implement shared pagetables and switch from 4 to 3 levels page memory system. RISC-V ISA has only single page table base register for both kernel and user addresses translation. Before this commit we were using an extra (4th) level of pagetables for switching between kernel and user pagetables, but then realized FPGA hardware has 3-level page system hardcoded. It is also become clear that the bitfile synthesized for 4-level system is untested/broken, so we can't use extra level for switching. We are now share level 1 of pagetables between kernel and user VA. This requires to keep track of all the user pmaps created and once we adding L1 page to kernel pmap we have to add it to all the user pmaps. o Change the VM layout as we must have topmost bit to be 1 in the selected page system for kernel addresses and 0 for user addresses. o Implement pmap_kenter_device(). o Create the l3 tables for the early devmap. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
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8d7e7a98 |
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17-Dec-2015 |
Ruslan Bukin <br@FreeBSD.org> |
Import RISC-V machine headers. This is a minimal set required to compile kernel and userland. Reviewed by: andrew, imp, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4554
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