sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/
Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/
Remove /\n+#if.*\n#endif.*\n+/
Remove /^#if.*\n#endif.*\n/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/

Sponsored by: Netflix

sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of BSD-2-Clause.

Discussed with: pfg
MFC After: 3 days
Sponsored by: Netflix

mmc(4): Don't call bridge driver for timings not requiring tuning

The original idea behind calling into the bridge driver was to have the
logic deciding whether tuning is actually required for a particular bus
timing in a given slot as well as doing the sanity checking only on the
controller layer which also generally is better suited for these due to
say SDHCI_SDR50_NEEDS_TUNING. On another thought, not every such driver
should need to check whether tuning is required at all, though, and not
everything is SDHCI in the first place.
Adjust sdhci{,_fsl_fdt}(4) accordingly, but keep sdhci_generic_tune() a
bit cautious still.

Add support for Rockchip RK3568 SDHCI controller.

sdhci_card_task: d is only used in the non-MMCCAM case.

Revert "sdhci: extend bus_dma_tag boundary to 64-bit space"

This reverts commit 7d8700bc291b4b3be1a592cae539f9e682592d9d.

Reason for revert: the patch is incomplete. 64-bit operation
is supported fully in SDHCI v4.0, v3.0 does it only for ADMA mode.
This differentiation is missing and should be taken into consideration
in case the reverted code is re-introduced.

Reported by: mmel

sdhci: fix dumping support in MMCCAM configuration

This change fixes interaction with recently added sddadump.

MFC after: 1 week

sdhci: plug set-but-not-unused vars

Sponsored by: Rubicon Communications, LLC ("Netgate")

sdhci: Provide devmethod for software reset

Some sdhci controllers require custom software reset logic. Accommodate
this need by introducing a new SDHCI_RESET devmethod. Move the existing
reset logic into sdhci_generic_reset and use it as a default for the
aforementioned method.

Obtained from: Semihalf
Sponsored by: Alstom Group
Differeential revision: https://reviews.freebsd.org/D32704

sdhci: Fix crash caused by M_WAITOK in sdhci dumps

In some contexts it is illegal to wait for memory allocation, causing
kernel panic. By default sbuf_new passes M_WAITOK to malloc,
which caused crashes when sdhci_dumpcaps or sdhci_dumpregs was callend in
non sutiable context.

Add SBUF_NOWAIT flag to sbuf_new to fix this.

Obtained from: Semihalf
Differential revision: https://reviews.freebsd.org/D32075

sdhci: add a missing newline

sdhci: add sysctls to dump sdhci registers and capabilites

Add sysctls dev.sdhci.X.slotY.dumpregs and dev.sdhci.X.slotY.dumpcaps
which dumps sdhci registers or capabilities.

Obtained from: Semihalf
Reviewed by: mw
Differential revision: https://reviews.freebsd.org/D31406

Call wakeup() with the lock held to avoid missed wakeup races.

Submitted by: luiz
Sponsored by: Rubicon Communications, LLC ("Netgate")

MMCCAM: fix a panic after cam_sim_alloc_dev() removal in sdhci.c

During the removal of cam_sim_alloc_dev() in
aeb04e88f51a706ef4b6a380bf5e82d15203fb6a for sdhci.c and the
follow-up build-fix in a72af82e3169fcacfedf9047120679300a4296f8
slot->dev and slot->bus got mixed up for MMCCAM; slot->dev is
only used in the !MMCCAM case so is uninitialised here leading to
a panic; switch back to slot->bus to return to the status quo.

Reviewed by: imp (ack on arm@)
X-Differential Revision: https://reviews.freebsd.org/D30857

cam: Fix GENERIC-MMCCAM build

Fix forgotten argument and type error. MMCCAM isn't enabled by default,
and I'd mistakenly thought it was, so these went undetected precommit.

Sponsored by: Netflix

sdhci: stop using cam_sim_alloc_dev

Sponsored by: Netflix
Differential Revision: https://reviews.freebsd.org/D30857

sdhci: allow setting MMC capabilities before sdhci_init_slot

With this change the host controller drivers can set the MMC capabilities
(e.g. using mmc_fdt_parse() helper) before calling sdhci_init_slot().
This way the configuration dump (eg. in bootverbose) can include the
possible additional information.

Reviewed by: manu
Obtained from: Semihalf
Sponsored by: Marvell
Differential Revision: https://reviews.freebsd.org/D30561
MFC after: 2 weeks

sdhci: extend bus_dma_tag boundary to 64-bit space

This patch adds support for the SDHCI_CAN_DO_64BIT
capability, so that to allow 64-bit DMA operation
for the controllers which support this feature.

Reviewed by: manu
Obtained from: Semihalf
Sponsored by: Marvell
Differential Revision: https://reviews.freebsd.org/D30560
MFC after: 2 weeks

mmccam: Add two new XPT for MMC and use them in mmc_sim and sdhci

For the discovery phase of SD/eMMC we need to do some transaction in a async
way.
The classic CAM XPT_{GET,SET}_TRAN_SETTING cannot be used in a async way.
This also allow us to split the discovery phase into a more complete state
machine and we don't mtx_sleep with a random number to wait for completion
of the tasks.
For mmc_sim we now do the SET_TRAN_SETTING in a taskqueue so we can call
the needed function for regulators/clocks without the cam lock(s). This part is
still needed to be done for sdhci.
We also now save the host OCR in the discovery phase as it wasn't done before and
only worked because the same ccb was reused.

Reviewed by: imp, kibab, bz
Differential Revision: https://reviews.freebsd.org/D30038

Make MAXPHYS tunable. Bump MAXPHYS to 1M.

Replace MAXPHYS by runtime variable maxphys. It is initialized from
MAXPHYS by default, but can be also adjusted with the tunable kern.maxphys.

Make b_pages[] array in struct buf flexible. Size b_pages[] for buffer
cache buffers exactly to atop(maxbcachebuf) (currently it is sized to
atop(MAXPHYS)), and b_pages[] for pbufs is sized to atop(maxphys) + 1.
The +1 for pbufs allow several pbuf consumers, among them vmapbuf(),
to use unaligned buffers still sized to maxphys, esp. when such
buffers come from userspace (*). Overall, we save significant amount
of otherwise wasted memory in b_pages[] for buffer cache buffers,
while bumping MAXPHYS to desired high value.

Eliminate all direct uses of the MAXPHYS constant in kernel and driver
sources, except a place which initialize maxphys. Some random (and
arguably weird) uses of MAXPHYS, e.g. in linuxolator, are converted
straight. Some drivers, which use MAXPHYS to size embeded structures,
get private MAXPHYS-like constant; their convertion is out of scope
for this work.

Changes to cam/, dev/ahci, dev/ata, dev/mpr, dev/mpt, dev/mvs,
dev/siis, where either submitted by, or based on changes by mav.

Suggested by: mav (*)
Reviewed by: imp, mav, imp, mckusick, scottl (intermediate versions)
Tested by: pho
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D27225

sdhci: mmccam: Update vccq in the driver ios

Otherwise we always report that the card is running at 1.2V.

sdhci: Only print mmccam debug code if hw.sdhci.debug is > 1

mmccam: Add a generic mmccam_start_discovery function

This is a generic function start a scan request for the given
cam_sim.
Other driver can now just use this function to request a new rescan.

Submitted by: kibab

Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many)

r357614 added CTLFLAG_NEEDGIANT to make it easier to find nodes that are
still not MPSAFE (or already are but aren’t properly marked).
Use it in preparation for a general review of all nodes.

This is non-functional change that adds annotations to SYSCTL_NODE and
SYSCTL_PROC nodes using one of the soon-to-be-required flags.

Mark all obvious cases as MPSAFE. All entries that haven't been marked
as MPSAFE before are by default marked as NEEDGIANT

Approved by: kib (mentor, blanket)
Commented by: kib, gallatin, melifaro
Differential Revision: https://reviews.freebsd.org/D23718

No need to have an extra layer of indirection here. Call the sdhci_cam_requiest
routine directly when handling a MMIO request.

Create a convenince wrapper to fill in a CAM_PATH_INQ request for MMC sims. Pass
in the parameters needed for the different sims, but it's almost all identical.

Relax the sdhci(4) check that filters out the 1.8v voltage option unless
the slot is flagged as 'embedded'.

The features related to embedded and shared slots were added in v3.0 of
the sdhci spec. Hardware prior to v3 sometimes supported 1.8v on non-
removable devices in embedded systems, but had no way to indicate that
via the standard sdhci registers (instead they use out of band metadata
such as FDT data).

This change adds the controller specification version to the check for
whether to filter out the 1.8v selection. On older hardware, the 1.8v
option is allowed to remain. On 3.0 or later it still requires the
embedded-slot flag to remain.

This is part of the fix for PR 241301 (eMMC not detected on Beaglebone).
Changes to the sdhci_ti driver are also needed for a full fix.

PR: 241301

Allow the sdhci timeout sysctl var to be set as a tunable. Also, add a
missing newline in a warning printf.

Improve sdhci slot_printf() debug printing.

Currently slot_printf() uses two printf() calls to print the
device-slot name, and actual message. When other printf()s are
ongoing in parallel this can lead to interleaved message on the console,
which is especially unhelpful for debugging or error messages.

Take a hit on the stack and vsnprintf() the message to the buffer.
This way it can be printed along with the device-slot name in one go
avoiding console gibberish.

Reviewed by: marius
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D19747

Introduce sim_dev and cam_sim_alloc_dev().

Add cam_sim_alloc_dev() as a wrapper to cam_sim_alloc() which takes
a device_t instead of the unit_number (which we can derive from the
dev again).

Add device_t sim_dev to struct cam_sim. It will be used to pass through
the bus for cases when both sides of CAM speak newbus already and we want
to link them (yet make the calls through CAM for now).

SDIO will be the first consumer of this. For that make use of
cam_sim_alloc_dev() in sdhci under MMCCAM.

This will also allow people to start iterating more on the idea
to newbus-ify CAM without changing 50+ device drivers from the start.
Also to be clear there are callers to cam_sim_alloc() which do not
have a device_t (e.g., XPT) or provide their own unit number so we cannot
simply switch the KPI entirely.

Submitted by: kibab (original idea, see https://reviews.freebsd.org/D12467)
Reviewed by: imp, chuck
MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D19746

Improve error/debug messages in sdhci.c

When starting a command also print the opcode and flags.
More consitently print flags as hex.
Use slot_printf rather than printf in one case.

MFC after: 6 weeks
Reviewed by: marius, kibab, imp
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D19748

Implement CMD53 block mode support for SDHCI and AllWinner-based boards

If a custom block size requested, use it, otherwise revert to the previous logic
of using just a data size if it's less than MMC_BLOCK_SIZE, and MMC_BLOCK_SIZE otherwise.

Reviewed by: bz
Approved by: imp (mentor)
Differential Revision: https://reviews.freebsd.org/D19783

Use information about max data size that the controller is able to operate

Using DFLTPHYS/MAXPHYS is not always OK, instead make it possible for the
controller driver to provide maximum data size to MMCCAM, and use it there.

The old stack already does this.

Reviewed by: manu
Approved by: imp (mentor)
Differential Revision: https://reviews.freebsd.org/D15892

Whitespace cleanup in sdhci.c

No functional changes. Replace whitespace by tabs, indent with 4 spaces,
coalesce multi-line shorter than 80 characters,

MFC after: 2 weeks
Sponsored by: The FreeBSD Foundation

o Don't allocate resources for SDMA in sdhci(4) if the controller or the
front-end doesn't support SDMA or the latter implements a platform-
specific transfer method instead. While at it, factor out allocation
and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to
keep the code more readable when adding support for ADMA variants.

o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum
of 512 KiB instead of using a fixed 4-KiB-buffer. With the default
MAXPHYS of 128 KiB and depending on the controller and medium, this
reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on
sequential reads while an increase of throughput of up to ~84 % was
seen.

Front-ends for broken controllers that only support an SDMA buffer
boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY
and supply a size via struct sdhci_slot. According to Linux, only
Qualcomm MSM-type SDHCI controllers are affected by this, though.

Requested by: Shreyank Amartya (unconditional bump to 512 KiB)

o Introduce a SDHCI_DEPEND macro for specifying the dependency of the
front-end modules on the sdhci(4) one and bump the module version
of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order
to ensure that all components are in sync WRT struct sdhci_slot.

o In sdhci(4):
- Make pointers const were applicable,
- replace a few device_printf(9) calls with slot_printf() for
consistency, and
- sync some local functions with their prototypes WRT static.

Add a quirk handling for AMDI0040 controllers allowing them to do HS400.

Submitted by: Shreyank Amartya (original version)

- Explicitly compare a pointer to NULL. The __builtin_expect() of clang
3.4.1 otherwise isn't able to cope with the expression.
- Fix a nearby whitespace bug.

Approved by: re (gjb, kib)

- According to section 2.2.5 of the SDHCI specification version 4.20,
SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write
commands without data length information, so don't unconditionally
set this bit. The result matches what e. g. Linux does.
- Section 2.2.19 of the SDHCI specification version 4.20 states that
SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set
and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is
cleared (differing silicon behavior is specifically allowed, though).
Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR.
While at it, use the 16-bit accessor rather than the 32-bit one for
reading the 16-bit SDHCI_ACMD12_ERR.
- SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so
clear it explicitly.
- Add missing prototypes and sort them.

Fix a bug introduced in r327339; at the point in time re-tuning is
executed, the interrupt aggregation code might have disabled the
SDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE bits in slot->intmask
and the SDHCI_SIGNAL_ENABLE register respectively. So when restoring
the interrupt masks based on the previous contents of slot->intmask
in sdhci_exec_tuning(), ensure that the SDHCI_INT_ENABLE register
doesn't lose these two bits.
While at it and in the spirit of r327339, let sdhci_tuning_intmask()
set the tuning error and re-tuning interrupt bits based on the
SDHCI_TUNING_ENABLED rather than the SDHCI_TUNING_SUPPORTED flag
being set, i. e. only when (re-)tuning is actually used. Currently,
this changes makes no net difference, though.

- There is no need to keep the tuning error and re-tuning interrupts
enabled (though, no interrupt generation enabled for them) all the
time as soon as (re-)tuning is supported; only enable them and let
them generate interrupts when actually using (re-)tuning.
- Also disable all interrupts except SDHCI_INT_DATA_AVAIL ones while
executing tuning and not just their signaling.

sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Rename sdhci_cam_start_slot() into sdhci_start_slot()

This change allows to just call sdhci_start_slot() in SDHCI drivers
and not to think about which stack handles the operation.

As a side effect, this will also fix MMCCAM with sdhci_acpi driver.

Approved by: imp (mentor)
Differential Revision: https://reviews.freebsd.org/D12471

- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE}
for embedded slots. Fail in the sdhci(4) initialization for slot type
shared, which is completely unsupported by this driver at the moment. [1]
For Intel eMMC controllers, taking the embedded slot type into account
obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk
entries.
- Hide the 1.8 V VDD capability when the slot is detected as non-embedded,
as the SDHCI specification explicitly states that 1.8 V VDD is applicable
to embedded slots only. [2]
- Define some easy bits of the SDHCI specification v4.20. [3]
- Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().

Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]

o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to
sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of:
- Correcting and extending the infrastructure for negotiating and
enabling post-DDR52 modes already added as part of r315598. In
fact, HS400ES now should work as well but hasn't been activated
due to lack of corresponding hardware.
- Adding support executing standard SDHCI initial tuning as well
as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I
SD card modes. Currently, corresponding methods are only hooked
up to the ACPI and PCI front-ends of sdhci(4), though. Moreover,
sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD
layer in order to not break operations with other sdhci(4) front-
ends. Likewise, sdhci(4) now no longer offers modes requiring the
set_uhs_timing method introduced in r315598 to be implemented/
hooked up (previously, this method was used with DDR52 only, which
in turn is only available with Intel controllers so far, i. e. no
such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ
support and the switch_vccq method.
- Addition of locking to the IOCTL half of mmcsd(4) to prevent races
with detachment and suspension, especially since it's required to
immediately switch away from RPMB partitions again after an access
to these (so re-tuning can take place anew, given that the current
eMMC specification v5.1 doesn't allow tuning commands to be issued
with a RPMB partition selected). Therefore, the existing part_mtx
lock in the mmcsd(4) softc is additionally renamed to disk_mtx in
order to denote that it only refers to the disk(9) half, likewise
for corresponding macros.

On the system where the addition of DDR52 support increased the read
throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields
~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than
quadrupled compared to pre-r315598.

Also, with the advent of (re-)tuning support, most infrastructure
necessary for SD card UHS-I modes up to SDR104 now is also in place.
Note, though, that the standard SDHCI way of (re-)tuning is special
in several ways, which also is why sending the actual tuning requests
to the device is part of sdhci(4). SDHCI implementations not following
the specification, MMC and non-SDHCI SD card controllers likely will
use a generic implementation in the MMC/SD layer for executing tuning,
which hasn't been written so far, though.

However, in fact this isn't a feature-only change; there are boards
based on Intel Bay Trail where DDR52 is problematic and the suggested
workaround is to use HS200 mode instead. So far exact details are
unknown, however, i. e. whether that's due to a defect in these SoCs
or on the boards.

Moreover, due to the above changes requiring to be aware of possible
MMC siblings in the fast path of mmc(4), corresponding information
now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(),
mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now
all are guaranteed to operate on the same set of devices as there no
longer is any use of device_get_children(9), which can fail in low
memory situations. Likewise, mmc_calculate_clock() now longer will
trigger a panic due to the latter.

o Fix a bug in the failure reporting of mmcsd_delete(); in case of an
error when the starting block of a previously stored erase request
is used (in order to be able to erase a full erase sector worth of
data), the starting block of the newly supplied bio_pblkno has to be
returned for indicating no progress. Otherwise, upper layers might
be told that a negative number of BIOs have been completed, leading
to a panic.

o Fix 2 bugs on resume:
- Things done in fork1(9) like the acquisition of an SX lock or the
sleepable memory allocation are incompatible with a MTX_DEF taken.
Thus, mmcsd_resume() must not call kproc_create(9), which in turn
uses fork1(9), with the disk_mtx (formerly part_mtx) held.
- In mmc_suspend(), the bus is powered down, which in the typical
case of a device being selected at the time of suspension, causes
the device deselection as part of the bus acquisition by mmc(4) in
mmc_scan() to fail as the bus isn't powered up again before later
in mmc_go_discovery(). Thus, power down with the bus acquired in
mmc_suspend(), which will trigger the deselection up-front.

o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]

o Fix missing variable initialization in mmc_switch_status(). [2]

o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]

o Handle the case of device_add_child(9) failing, for example due to
a memory shortage, gracefully in mmc(4) and sdhci(4), including not
leaking memory for the instance variables in case of mmc(4) (which
might or might not fix [4] as the latter problem has been discovered
independently).

o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd()
gracefully instead of calling panic(9).

o Again, check and handle the return values of some additional function
calls in mmc(4) instead of assuming that everything went right or mark
non-fatal errors by casting the return value to void.

o Correct a typo in the Linux IOCTL compatibility; it should have been
MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.

o Now that we are reaching ever faster speeds (more improvement in this
regard is to be expected when adding ADMA support to sdhci(4)), apply
a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging
to be off or caching erase sector and maximum data sizes as well support
of block addressing in mmsd(4) (instead of doing 2 indirections on every
read/write request for determining the maximum data size for example).

Reported by: Coverity
CID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]

Better contain MMCCAM parts of this file
Remove some useless to the general user debugs
Put debugs under sdhci_debug.
Fix some style(9) regressions

Submitted by: marius@

Back out enabling the card interrupt detection bit. It is not ready to
commit.

Noticed by: marius@

An MMC/SD/SDIO stack using CAM

Implement the MMC/SD/SDIO protocol within a CAM framework. CAM's
flexible queueing will make it easier to write non-storage drivers
than the legacy stack. SDIO drivers from both the kernel and as
userland daemons are possible, though much of that functionality will
come later.

Some of the CAM integration isn't complete (there are sleeps in the
device probe state machine, for example), but those minor issues can
be improved in-tree more easily than out of tree and shouldn't gate
progress on other fronts. Appologies to reviews if specific items
have been overlooked.

Submitted by: Ilya Bakulin
Reviewed by: emaste, imp, mav, adrian, ian
Differential Review: https://reviews.freebsd.org/D4761

merge with first commit, various compile hacks.

Correct a typo in the comment part of r320577, later on copied into
the commit message; as actually implemented, the intent is to retry
up to 2 ms for controllers to enable bus power.
Noticed by: ian@, rgrimes@

Additional note: Among others, the problem addressed by r320577 is
the APL32 ("Storage Controllers May Not Be Power Gated") erratum.
Hopefully, along with r318282, r320577 works around the remaining
problems seen with Intel Apollo Lake eMMC and SDXC controllers.

Retry up to 20 ms to enable bus power as at least with some Intel
SDHCI/eMMC controllers the first attempt after a D3 to D0 transition,
i. e. when the firmware has put the devices into D3 state before,
can fail.

Fix typo in Driver Type A/C/D capability checks in sdhci.

Use the SDHCI_CAN_DRIVE_TYPE_A/_C/_D masks to check for Driver Type support,
instead of using the SDHCI_CTRL2_DRIVER_TYPE_A/_C/_D values which are meant
for setting the Driver Type in the HOST_CONTROL2 register.

Approved by: adrian (mentor), jmcneill
Differential Revision: https://reviews.freebsd.org/D10999

Add a new SDHCI quirk, SDHCI_QUIRK_BROKEN_AUTO_STOP, to workaround
controllers that do not support or have broken ACMD12 implementations.

Reviewed by: jmcneill
Obtained from: NetBSD
MFC after: 2 weeks
Sponsored by: Rubicon Communications, LLC (Netgate)
Differential Revision: https://reviews.freebsd.org/D10602

o Add support for eMMC DDR bus speed mode at 52 MHz to sdhci(4) and
mmc(4). For the most part, this consists of support for:
- Switching the signal voltage (VCCQ) to 1.8 V or (if supported
by the host controller) to 1.2 V,
- setting the UHS mode as appropriate in the SDHCI_HOST_CONTROL2
register,
- setting the power class in the eMMC device according to the
core supply voltage (VCC),
- using different bits for enabling a bus width of 4 and 8 bits
in the the eMMC device at DDR or higher timings respectively,
- arbitrating timings faster than high speed if there actually
are additional devices on the same MMC bus.

Given that support for DDR52 is not denoted by SDHCI capability
registers, availability of that timing is indicated by a new
quirk SDHCI_QUIRK_MMC_DDR52 and only enabled for Intel SDHCI
controllers so far. Generally, what it takes for a sdhci(4)
front-end to enable support for DDR52 is to hook up the bridge
method mmcbr_switch_vccq (which especially for 1.2 V signaling
support is chip/board specific) and the sdhci_set_uhs_timing
sdhci(4) method.

As a side-effect, this change also fixes communication with
some eMMC devices at SDR high speed mode with 52 MHz due to
the signaling voltage and UHS bits in the SDHCI controller no
longer being left in an inappropriate state.

Compared to 52 MHz at SDR high speed which typically yields
~45 MB/s with the eMMC chips tested, throughput goes up to
~80 MB/s at DDR52.

Additionally, this change already adds infrastructure and quite
some code for modes up to HS400ES and SDR104 respectively (I did
not want to add to much stuff at a time, though). Essentially,
what is still missing in order to be able to activate support
for these latter is is support for and handling of (re-)tuning.

o In sdhci(4), add two tunables hw.sdhci.quirk_clear as well as
hw.sdhci.quirk_set, which (when hooked up in the front-end)
allow to set/clear sdhci(4) quirks for debugging and testing
purposes. However, especially for SDHCI controllers on the
PCI bus which have no specific support code so far and, thus,
are picked up as generic SDHCI controllers, hw.sdhci.quirk_set
allows for setting the necessary quirks (if required).

o In mmc(4), check and handle the return values of some more
function calls instead of assuming that everything went right.
In case failures actually are not problematic, indicate that
by casting the return value to void.

Reviewed by: jmcneill

Again, fixes regarding style(4), to comments, includes and unused
parameters.

- Adds macros for the content of SDHCI_ADMA_ERR and SDHCI_HOST_CONTROL2
registers.
- Add slot type capability bits. These bits should allow recognizing
removable card slots, embedded cards and shared buses (shared bus
supposedly is always comprised of non-removable cards).
- Dump CAPABILITIES2, ADMA_ERR, HOST_CONTROL2 and ADMA_ADDRESS_LO
registers in sdhci_dumpregs().
- The drive type support flags in the CAPABILITIES2 register are for
drive types A,C,D, drive type B is the default setting (value 0) of
the drive strength field in the SDHCI_HOST_CONTROL2 register.

Obtained from: DragonFlyBSD (9e3c8f63, 455bd1b1)

- Add support for eMMC "partitions". Besides the user data area, i. e.
the default partition, eMMC v4.41 and later devices can additionally
provide up to:
1 enhanced user data area partition
2 boot partitions
1 RPMB (Replay Protected Memory Block) partition
4 general purpose partitions (optionally with a enhanced or extended
attribute)

Of these "partitions", only the enhanced user data area one actually
slices the user data area partition and, thus, gets handled with the
help of geom_flashmap(4). The other types of partitions have address
space independent from the default partition and need to be switched
to via CMD6 (SWITCH), i. e. constitute a set of additional "disks".

The second kind of these "partitions" doesn't fit that well into the
design of mmc(4) and mmcsd(4). I've decided to let mmcsd(4) hook all
of these "partitions" up as disk(9)'s (except for the RPMB partition
as it didn't seem to make much sense to be able to put a file-system
there and may require authentication; therefore, RPMB partitions are
solely accessible via the newly added IOCTL interface currently; see
also below). This approach for one resulted in cleaner code. Second,
it retains the notion of mmcsd(4) children corresponding to a single
physical device each. With the addition of some layering violations,
it also would have been possible for mmc(4) to add separate mmcsd(4)
instances with one disk each for all of these "partitions", however.
Still, both mmc(4) and mmcsd(4) share some common code now e. g. for
issuing CMD6, which has been factored out into mmc_subr.c.

Besides simply subdividing eMMC devices, some Intel NUCs having UEFI
code in the boot partitions etc., another use case for the partition
support is the activation of pseudo-SLC mode, which manufacturers of
eMMC chips typically associate with the enhanced user data area and/
or the enhanced attribute of general purpose partitions.

CAVEAT EMPTOR: Partitioning eMMC devices is a one-time operation.

- Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications. However, quite some work is
left to be done in this regard; all other R1B-type commands done by
the MMC layer also should be followed by a SEND_STATUS (CMD13), the
erase timeout calculations/handling as documented in specifications
are entirely ignored so far, the MMC layer doesn't provide timeouts
applicable up to the bridge drivers and at least sdhci(4) currently
is hardcoding 1 s as timeout for all command types unconditionally.
Let alone already available return codes often not being checked in
the MMC layer ...

- Add an IOCTL interface to mmcsd(4); this is sufficiently compatible
with Linux so that the GNU mmc-utils can be ported to and used with
FreeBSD (note that due to the remaining deficiencies outlined above
SANITIZE operations issued by/with `mmc` currently most likely will
fail). These latter will be added to ports as sysutils/mmc-utils in
a bit. Among others, the `mmc` tool of the GNU mmc-utils allows for
partitioning eMMC devices (tested working).

- For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.

- Let mmcsd.ko depend on mmc.ko. Additionally, bump MMC_VERSION as at
least for some of the above a matching pair is required.

- In the ACPI front-end of sdhci(4) describe the Intel eMMC and SDXC
controllers as such in order to match the PCI one.
Additionally, in the entry for the 80860F14 SDXC controller remove
the eMMC-only SDHCI_QUIRK_INTEL_POWER_UP_RESET.

OKed by: imp
Submitted by: ian (mmc_switch_status() implementation)

o Another round fixes for mmc(4), mmcsd(4) and sdhci(4) regarding
comments, marking unused parameters as such, style(9), whitespace,
etc.
o In the mmc(4) bridges and sdhci(4) (bus) front-ends:
- Remove redundant assignments of the default bus_generic_print_child
device method (I've whipped these out of the tree as part of r227843
once, but they keep coming back ...),
- use DEVMETHOD_END,
- use NULL instead of 0 for pointers.
o Trim/adjust includes.

Fix some more overly long lines, whitespace and other bugs according to
style(9) as well as spelling in comments.

Fix overly long lines, whitespace and other bugs according to style(9).

Add sdhci_handle_card_present_locked() that can be called from the interrupt
handler which already holds the mutex, and have sdhci_handle_card_present()
be just a tiny wrapper that does the locking for external callers.

This should fix the recursive locking panics seen on rpi3.

Reported by: Shawn Webb

- Add support for Intel Apollo Lake and Bay Trail eMMC controllers.
Besides slots always having non-removable media, these HCIs require
a custom hardware reset sequence after power-up.
- Flesh out the support for Intel Braswell eMMC controllers further.
Apart from also requiring said reset code, the timeout clock needs to
be hardcoded to 1 MHz for these.
Both the special reset and timeout clock handlings are implemented as
global sdhci(4) quirks as the same treatment will be necessary for
Intel eMMC controllers attached via ACPI (once sdhci(4) grows such a
front-end).
- In sdhci_init_slot(), use the right capability field for determining
the announced bus width based on MMC_CAP_*_BIT_DATA.
- Correct inverted sdhci_pci_softc member comments added in r276469. [1]

Submitted by: Anton Yuzhaninov [1]
MFC after: 5 days

Add support for non-removable media, and a quirk to use polling to detect
card insert/remove events on controllers that don't implement the insert
and remove interrupts.

Bridge drivers can set a new slot option, SDHCI_NON_REMOVABLE, to indicate
non-removable media (such as eMMC). The sdhci driver will not enable
insert/remove interrupts, and sdhci_generic_get_card_present() will always
return true.

Bridge drivers can set a new quirk, SDHCI_QUIRK_POLL_CARD_PRESENT, and the
sdhci driver will not enable insert/remove interrupts, and instead will use
a callout to poll the card-present status at 5 Hz.

For bridge drivers that get notified of card insert/remove via gpio
interrupts, there is a new sdhci_handle_card_present() function they can
call from the gpio interrupt handler to inform the sdhci code of the event.

In addition to adding these new features, the existing code to debounce card
insertions was updated to use taskqueue_enqueue_timeout() instead of
scheduling a callout to do the taskqueue_enqueue(). There is also now a
comment explaining that insertion-debounce is what's going on -- it took me
a long time to realize that's what the old sdhci_card_delay() routine was
really doing. There is no functional difference between the old and new
debounce code (I hope!).

Now that the PRESENT_STATE register is only used for the inhibit bits loop
in this function, eliminate the state variable and restructure the loop to
read the register just once at the top of the loop.

Suggested by: skra

Add a new sdhci interface method, get_card_present().

Many embedded SoC controllers that are (more or less) sdhci-compatible don't
implement card detect, and the related values in the PRESENT_STATE register
aren't useful. A bridge driver can now implement get_card_present() to read
a gpio pin or whatever else is necessary for that system.

The default implementation reads the CARD_PRESENT bit from the PRESENT_STATE
register, so existing drivers will keep working (or keep not-fully-working,
since many drivers right now can't detect card insert/remove).

Toggle card insert/remove interrupt enable bits on events

Some controllers (namely Freescale's eSDHC, tested) will continue to assert
the card removed or card insert interrupts even after being handled. To work
around this, disable watching the interrupt that just occurred until the
opposite interrupt is triggered.

Linux has a similar change in its driver to address the same problem.

Add support for the BCM57765 card reader.

This patch adds support for the BCM57765[2] card reader function included in
Broadcom's BCM57766 ethernet/sd3.0 controller. This controller is commonly
found in laptops and Apple hardware (MBP, iMac, etc).

The BCM57765 chipset is almost fully compatible with the SD3.0 spec, but
does not support deriving a frequency below 781KHz from its default base
clock via the standard SD3.0-configured 10-bit clock divisor.

If such a divisor is set, card identification (which requires a 400KHz
clock frequency) will time out[1].

As a work-around, I've made use of an undocumented device-specific clock
control register to switch the controller to a 63MHz clock source when
targeting clock speeds below 781KHz; the clock source is likewise switched
back to the 200MHz clock when targeting speeds greater than 781KHz.

Additionally, this patch fixes a small sdhci_pci bug; the
sdhci_pci_softc->quirks flag was not copied to the sdhci_slot, resulting in
`quirk` behavior not being applied by sdhci.c.

[1] A number of Linux/FreeBSD users have noted that bringing up the chipsets'
associated ethernet interface will allow SD cards to enumerate (slowly).
This is a controller implementation side-effect triggered by the ethernet
driver's reading of the hardware statistics registers.

[2] This may also fix card detection when using the BCM57785 chipset, but I
don't have access to the BCM57785 chipset and can't verify.

I actually snagged some BCM57785 hardware recently (2012 Retina MacBook Pro)
and can confirm that this also fixes card enumeration with the BCM57785
chipset; with the patch, I can boot off of the internal sdcard reader.

PR: kern/203385
Submitted by: Landon Fuller <landon@landonf.org>

Raise the SDHCI timeout to 10 seconds and add a sysctl to allow changing
this value at runtime.

The SD card specification says that a block write or a block erase can take
up to 250ms to complete and thus, under some circumstances, the existent 2
seconds timeout was triggering with normal usage.

This change fixes the sporadic controller timeout that happens on RPi and
RPi 2.

Discussed with: ian (some time ago)

Detect, report and use 8-bit bus if is available.

Differential Revision: https://reviews.freebsd.org/D1921
Submitted by: Michal Meloun

Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT. Apparently some
sdhci controllers, such as the one on a Raspberry Pi, mishandle the signal
timing in high speed signaling mode, but run just fine in standard mode
with the bus running at frequencies between 25-50MHz (which shouldn't work).

This is the solution adopted by U-Boot and other OSes (linux and *BSD)
for the timeouts on Raspberry Pi boards with certain SD cards. Some
research shows that this quirk is also used on a few other boards, so the
fix is a generic quirk instead of being in the RPi-specific driver code.

This change is based on information discovered by Michal Meloun.

Handle the possibility that SDHCI_PLATFORM_START_TRANSFER() can fail, by
moving the handling of curcmd->error != 0 to the end of the interrupt
handler. Also make sdhci_finish_data() idempotent by moving the setting
of slot->data_done = 1 down past the point where the busdma buffer is
unmapped. This allows for the possibility that the finish routine can
get called from multiple places when handling errors.

Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.

The zero is apparently from a stale snapshot of the internal state presented
in the interface register, and leads to a false indication that the reset
is complete when it either hasn't started yet or is in-progress. The
workaround is to first loop until the bit is seen as asserted, then do the
normal loop waiting to see it de-asserted.

Submitted by: Michal Meloun <meloun@miracle.cz>

When command and data interrupts have been aggregated together, don't do
the data-completed processing if a command-error interrupt is also asserted.

Reviewed by: Michal Meloun <meloun@miracle.cz>

- Nuke unused sdhci_softc.
- Static'ize sdhci_debug local to sdhci.c.
- Const'ify PCI device description strings.
- Nuke redundant resource ID members from sdhci_pci_softc.
- Nuke unused hw.sdhci_pci.debug tunable.
- Add support for using MSI instead of INTx, controllable via the tunable
hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD
controller.
- Use NULL instead of 0 for pointers.

MFC after: 3 days

Pull in r267961 and r267973 again. Fix for issues reported will follow.

Revert r267961, r267973:

These changes prevent sysctl(8) from returning proper output,
such as:

1) no output from sysctl(8)
2) erroneously returning ENOMEM with tools like truss(1)
or uname(1)
truss: can not get etype: Cannot allocate memory

Extend the meaning of the CTLFLAG_TUN flag to automatically check if
there is an environment variable which shall initialize the SYSCTL
during early boot. This works for all SYSCTL types both statically and
dynamically created ones, except for the SYSCTL NODE type and SYSCTLs
which belong to VNETs. A new flag, CTLFLAG_NOFETCH, has been added to
be used in the case a tunable sysctl has a custom initialisation
function allowing the sysctl to still be marked as a tunable. The
kernel SYSCTL API is mostly the same, with a few exceptions for some
special operations like iterating childrens of a static/extern SYSCTL
node. This operation should probably be made into a factored out
common macro, hence some device drivers use this. The reason for
changing the SYSCTL API was the need for a SYSCTL parent OID pointer
and not only the SYSCTL parent OID list pointer in order to quickly
generate the sysctl path. The motivation behind this patch is to avoid
parameter loading cludges inside the OFED driver subsystem. Instead of
adding special code to the OFED driver subsystem to post-load tunables
into dynamically created sysctls, we generalize this in the kernel.

Other changes:
- Corrected a possibly incorrect sysctl name from "hw.cbb.intr_mask"
to "hw.pcic.intr_mask".
- Removed redundant TUNABLE statements throughout the kernel.
- Some minor code rewrites in connection to removing not needed
TUNABLE statements.
- Added a missing SYSCTL_DECL().
- Wrapped two very long lines.
- Avoid malloc()/free() inside sysctl string handling, in case it is
called to initialize a sysctl from a tunable, hence malloc()/free() is
not ready when sysctls from the sysctl dataset are registered.
- Bumped FreeBSD version to indicate SYSCTL API change.

MFC after: 2 weeks
Sponsored by: Mellanox Technologies

When changing the sd bus clock divisor, clear just the bus clock enable bit
before changing the divisor bits in the register. We were writing a zero
to the register, which clears the enable, but also cleared the divisor bits
at the same time. That's a violation of the sdhci spec, which says the
divisor can only be changed when the clock is disabled. This has worked
okay on most hardware for years, but the TI OMAP controller would misbehave
after changing the divisor improperly.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>

After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA
rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing
any possibility of recovering from the error.

Also, double the timeout to 2 seconds. Despite what the SD spec says about
all transactions completing in 250ms or less, I have a card which sometimes
takes more than a second to complete a write.

Add timeout logic to sdhci, separate from the timeouts done by the hardware.

If the hardware is not in a good state (like maybe clocks aren't running
because of a configuration glitch) its timeout clock may also not work
correctly, and the next command sent will hang that thread forever. The
thread in question is usually the one and only thread (at init time) or
a bio queue worker thread whose lockup will eventually lead to the whole
system locking up when it runs out of buffers.

No sd card command should take longer than 250ms. This new code establishes
a 1-second timeout to allow plenty of safety margin over that.

Increase the wait time for acquiring the bus from 10 to 250ms.

Normally it never needs to wait here at all; waiting is done at the end
of the prior command. When doing a crash dump, the normal interrupt
mechanism isn't used; instead the interrupt handler is called repeatedly
in a polling-like manner. This can subvert hardware-specific drivers
and lead to trying to start a new command while the previous command is
still busy on the bus. Since the SD spec says the longest a card can
take to execute any command is 250ms, use that as a timeout.

Style changes and typos fixed.

Allow a hardware driver to pass clock frequencies into the sdhci driver.

The sdhci spec says that if the base or timeout clock frequency in the
capabilities register is zero, the driver must obtain the frequency "from
another source." This change defines that other source to be the low-level
hardware driver, which can pre-set the frequencies in slot.max_clk and
slot.timeout_clk before calling sdhci_init_slot().

This helps with a growing number of SoCs that have sdhci base clock
frequencies that either won't fit into the range allowed by the number of
bits available in the capabilities register, or the frequency is runtime-
configurable.

Add a new SDHCI_QUIRK_DONT_SHIFT_RESPONSE for hardware that pre-shifts
the response bits the way we do in software. While the hardware is just
doing the sensible thing rather than leaving it to the software, it's in
violation of the spec by doing so. Grrrr.

When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit. If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.

Add hooks for plugging platform-provided transfer backend.

In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
to start and finish transfer
- platform_will_handle - check whether transaction is
suitable for backend. If not - driver will fall back
to PIO mode.

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by: ian@

Remove accidentally committed debug panic(9) call

Disable debug accidentally enabled by previous commit

Various timing-related fixes:

- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
implementation. By re-implementing this method hardware
drivers can control frequency controller operates when
executing initialization sequence

- Get proper maximum clock frequency for SDHCI v3.0 and higher

Add new quirks:
- Data timeout is broken
- Data timeout uses SD clock
- Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0

Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface

No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.

Return back double spacing.

Fix typo in comment, should be MHz here.

Submitted by: Daan Vreeken <Daan vitsch.nl>

Add support for RICOH R5CE823 card reader, that can be found in
some Lenovo laptops.

The conroller needs a quirk to lower its frequency, and after
that it operates normally.

Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.

The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.

Fix read_ivar implementation for MMC and SD.

1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression
'*(int *)result = val' to assign to result which is uintptr_t *.
This does not work on big-endian 64 bit systems.

2. The media_size ivar is declared as 'off_t' which does not fit
into uintptr_t in 32bit systems, change this to long.

Submitted by: kanthms at netlogicmicro com (initial version)

Force DMA for controller found in Lenovo T510 (probably in others too).
This makes reads 10 times faster.

Discussed with: mav

A new jail(8) with a configuration file, to replace the work currently done
by /etc/rc.d/jail.

Add support for interruptless kernel dumping.

Fix read_ivar prototype.

Add hw.sdhci.debug sysctl to control debug level.

Cleanup msleep() arguments.
Move wakeup() out of the lock.

Forget current bus power settings on full reset. Chip must be reconfigured.

Do not issue command if there is no card, clock or power.
Controller will not detect command timeout without clock active.

Add controller suspend/resume support.

To be able to correctly suspend/resume with card inserted,
respective support should be also implemented at mmc and mmcsd layers.

Allow card reader bridge driver to report maximum supported transfer size.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.

Enable multiblock operations disabled before to follow at91_mci driver
limitations.

Reviewed by: imp@

Import sdhci (PCI SD Host Controller) driver.
Driver supports PCI devices with class 8 and subclass 5 according to
SD Host Controller Specification.

Update NOTES, enable module and static build.
Enable related mmc and mmcsd modules build.

Discussed on: mobile@, current@