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fdafd315 |
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24-Nov-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Automated cleanup of cdefs and other formatting Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
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#
685dc743 |
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16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Remove $FreeBSD$: one-line .c pattern Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
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#
4d846d26 |
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10-May-2023 |
Warner Losh <imp@FreeBSD.org> |
spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch up to that fact and revert to their recommended match of BSD-2-Clause. Discussed with: pfg MFC After: 3 days Sponsored by: Netflix
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#
ca43b2ae |
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05-May-2023 |
Mitchell Horne <mhorne@FreeBSD.org> |
hwpmc: trim obsolete Intel CPU and class defs No functional change. Reviewed by: jkoshy MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39904
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#
13260178 |
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02-Jun-2022 |
Alexander Motin <mav@FreeBSD.org> |
hwpmc: Add IDs for few more Intel Atom CPUs. MFC after: 1 month
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#
fe109d31 |
|
30-May-2022 |
Alexander Motin <mav@FreeBSD.org> |
hwpmc: Add basic Intel Alderlake CPUs support. The PMC subsystem is not designed for non-uniform CPU capabilities (P/E-cores are different), but at least several working architectural events like cpu_clk_unhalted.thread_p should be better than nothing. MFC after: 1 month
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#
913c07a0 |
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25-Nov-2021 |
Alexander Motin <mav@FreeBSD.org> |
hwpmc: Add IDs for Intel Comet/Ice/Tiger/Rocketlake CPUs. MFC after: 1 month
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#
8399d923 |
|
04-Aug-2021 |
Mitchell Horne <mhorne@FreeBSD.org> |
hwpmc_intel: assert for correct nclasses value This variable is set based on the exact CPU model detected. If this value is set too small, it could lead to a NULL-dereference from an improperly initialized pmc_rowindex_to_classdep array. Though it has been fixed, this was previously the case for Broadwell. Add two asserts to catch this in DEBUG kernels, as it represents a configuration error that may be hard to uncover otherwise. PR: 253687 Reported by: Zhenlei Huang <zlei.huang@gmail.com> Sponsored by: The FreeBSD Foundation
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#
4f35e8cb |
|
04-Aug-2021 |
Mitchell Horne <mhorne@FreeBSD.org> |
hwpmc: disable uncore class on Sandy Bridge and newer It was written for Nehalem and Westmere, with minor but incomplete updates for Sandy Bridge in 78d763a29b15. The uncore architecture changed significantly with this generation, bringing new layouts and locations for some MSRs. Misprogramming these MSRs in ucp_start_pmc() may panic the system, and this is trivially reproducible via pmcstat(8) on at least Broadwell and Haswell. Disable the class on these CPUs until it can be updated more completely and leave a TODO comment detailing some of the work required. Note that the nclasses value for Broadwell was already incorrect and doesn't need changing. The result is that any uncore events listed by pmcstat -L will no longer be allocatable, but this is already the case for newer generations of Intel CPUs. PR: 253687 Reported by: Zhenlei Huang <zlei.huang@gmail.com> Reviewed by: kib MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31389
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#
ef013cee |
|
14-Jul-2020 |
Ryan Moeller <freqlabs@FreeBSD.org> |
hwpmc: Always set pmc_cpuid to something pmc_cpuid was uninitialized for most AMD processor families. We can still populate this string for unimplemented families. Also added a CPUID_TO_STEPPING macro and converted existing code to use it. Reviewed by: mav MFC after: 2 weeks Sponsored by: iXsystems, Inc. Differential Revision: https://reviews.freebsd.org/D25673
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#
1791cad0 |
|
14-Jul-2020 |
Alexander Motin <mav@FreeBSD.org> |
Add stepping to the kern.hwpmc.cpuid string on x86. It follows the equivalent Linux change to be able to differentiate skylakex and cascadelakex, sharing the same model but not stepping. This fixes skylakex handling broken by r363144. MFC after: 6 days
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#
bbdddb80 |
|
24-Apr-2020 |
Alexander Motin <mav@FreeBSD.org> |
Add family 0x5F (Denverton) to PMC_CPU_INTEL_ATOM_GOLDMONT. According to the 325462-071US document, they should be the same. MFC after: 1 week
|
#
8e6d2a15 |
|
06-Apr-2020 |
Marcin Wojtas <mw@FreeBSD.org> |
Add hwpmc support for Intel Atom Goldmont microarchitecture Recognize new micro-architecture in hwpmc_intel driver. Based on Intel document 325462-071US. Tested with tools/test/hwpmc/pmctest.py on Atom E3930 SoC. Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: kib Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D24310
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#
d852f79b |
|
03-Jun-2019 |
Konstantin Belousov <kib@FreeBSD.org> |
hwpmc_intel: List all Silvermont ids. PR: 238310 Based on submission by: Masse Nicolas <nicolas.masse@stormshield.eu> MFC after: 1 week
|
#
e92a1350 |
|
31-May-2018 |
Matt Macy <mmacy@FreeBSD.org> |
hwpmc: remove unused pre-table driven bits for intel Intel now provides comprehensive tables for all performance counters and the various valid configuration permutations as text .json files. Libpmc has been converted to use these and hwpmc_core has been greatly simplified by moving to passthrough of the table values. The one gotcha is that said tables don't support pentium pro and and pentium IV. There's very few users of hwpmc on _amd64_ kernels on new hardware. It is unlikely that anyone is doing low level optimization on 15 year old Intel hardware. Nonetheless, if someone feels strongly enough to populate the corresponding tables for p4 and ppro I will reinstate the files in to the build. Code for the K8 counters and !x86 architectures remains unchanged.
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#
e6b475e0 |
|
11-May-2018 |
Matt Macy <mmacy@FreeBSD.org> |
hwpmc(9): Make pmclog buffer pcpu and update constants On non-trivial SMP systems the contention on the pmc_owner mutex leads to a substantial number of samples captured being from the pmc process itself. This change a) makes buffers larger to avoid contention on the global list b) makes the working sample buffer per cpu. Run pmcstat in the background (default event rate of 64k): pmcstat -S UNHALTED_CORE_CYCLES -O /dev/null sleep 600 & Before: make -j96 buildkernel -s >&/dev/null 3336.68s user 24684.10s system 7442% cpu 6:16.50 total After: make -j96 buildkernel -s >&/dev/null 2697.82s user 1347.35s system 6058% cpu 1:06.77 total For more realistic overhead measurement set the sample rate for ~2khz on a 2.1Ghz processor: pmcstat -n 1050000 -S UNHALTED_CORE_CYCLES -O /dev/null sleep 6000 & Collecting 10 samples of `make -j96 buildkernel` from each: x before + after real time: N Min Max Median Avg Stddev x 10 76.4 127.62 84.845 88.577 15.100031 + 10 59.71 60.79 60.135 60.179 0.29957192 Difference at 95.0% confidence -28.398 +/- 10.0344 -32.0602% +/- 7.69825% (Student's t, pooled s = 10.6794) system time: N Min Max Median Avg Stddev x 10 2277.96 6948.53 2949.47 3341.492 1385.2677 + 10 1038.7 1081.06 1070.555 1064.017 15.85404 Difference at 95.0% confidence -2277.47 +/- 920.425 -68.1574% +/- 8.77623% (Student's t, pooled s = 979.596) x no pmc + pmc running real time: HEAD: N Min Max Median Avg Stddev x 10 58.38 59.15 58.86 58.847 0.22504567 + 10 76.4 127.62 84.845 88.577 15.100031 Difference at 95.0% confidence 29.73 +/- 10.0335 50.5208% +/- 17.0525% (Student's t, pooled s = 10.6785) patched: N Min Max Median Avg Stddev x 10 58.38 59.15 58.86 58.847 0.22504567 + 10 59.71 60.79 60.135 60.179 0.29957192 Difference at 95.0% confidence 1.332 +/- 0.248939 2.2635% +/- 0.426506% (Student's t, pooled s = 0.264942) system time: HEAD: N Min Max Median Avg Stddev x 10 1010.15 1073.31 1025.465 1031.524 18.135705 + 10 2277.96 6948.53 2949.47 3341.492 1385.2677 Difference at 95.0% confidence 2309.97 +/- 920.443 223.937% +/- 89.3039% (Student's t, pooled s = 979.616) patched: N Min Max Median Avg Stddev x 10 1010.15 1073.31 1025.465 1031.524 18.135705 + 10 1038.7 1081.06 1070.555 1064.017 15.85404 Difference at 95.0% confidence 32.493 +/- 16.0042 3.15% +/- 1.5794% (Student's t, pooled s = 17.0331) Reviewed by: jeff@ Approved by: sbruno@ Differential Revision: https://reviews.freebsd.org/D15155
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#
718cf2cc |
|
27-Nov-2017 |
Pedro F. Giffuni <pfg@FreeBSD.org> |
sys/dev: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
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#
07ff05c2 |
|
13-Oct-2017 |
Ruslan Bukin <br@FreeBSD.org> |
o Support for Kabylake CPU PMCs (fall down to PMC_CPU_INTEL_SKYLAKE). o Fix bugs in events descriptions for Skylake, Skylake Xeon and Haswell. Reviewed by: kib Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D12654
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#
b99b705d |
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06-Sep-2017 |
Konstantin Belousov <kib@FreeBSD.org> |
Skylake server core PMC support for hwpmc(4). Reviewed by: emaste Sponsored by: The FreeBSD Foundation Hardware provided by: Intel MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D12221
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#
f19bae41 |
|
30-Nov-2015 |
Randall Stewart <rrs@FreeBSD.org> |
Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune guide (for the hacked up version I just made it so I could run the -T option). The Skylake CPU is not yet available (even though Intel is advertising it .. imagine that). The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-) Sponsored by: Netflix Inc.
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#
4a3690df |
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08-May-2015 |
John Baldwin <jhb@FreeBSD.org> |
Convert hwpmc(4) debug printfs over to KTR. Differential Revision: https://reviews.freebsd.org/D2487 Reviewed by: davide, emaste MFC after: 2 weeks Sponsored by: Norse Corp, Inc.
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#
bc346409 |
|
04-Apr-2015 |
Rui Paulo <rpaulo@FreeBSD.org> |
hwpmc: add initial Intel Broadwell support. The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month
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#
d95b3509 |
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13-Jan-2015 |
Randall Stewart <rrs@FreeBSD.org> |
Update the hwpmc driver to have the new type HASWELL_XEON. Also go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE to straighten out all the missing PMCs. We also add a new pmc tool pmcstudy, this allows one to run the various formulas from the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for IB/SB and Haswell. The tool also allows one to postulate your own formulas with any of the various PMC's. At some point I will enahance this to work with Brendan Gregg's flame-graphs so we can flamegraph various PMC interactions. Note the manual page also needs some work (lots of work) but gnn has committed to help me with that ;-) Reviewed by: gnn MFC after:1 month Sponsored by: Netflix Inc.
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#
49fe48ab |
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04-Jun-2014 |
Konstantin Belousov <kib@FreeBSD.org> |
For Xeon 7500 and 48XX (Nehalem EX and Westmere EX) variants of the Core i7 and Westmere processors, the uncore PMC subsystem is completely different from the uncore PMC on smaller versions of CPUs. Disable existing uncore hwpmc code for EX, otherwise non-existing MSRs are accessed. The cores PMCs seems to be identical for non-EX and EX, according to the SDM. Reviewed by: davide, fabient Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
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#
e8f021a3 |
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20-Mar-2014 |
Hiren Panchasara <hiren@FreeBSD.org> |
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014) Tested by: Olivier Cochard-Labbe <olivier@cochatrd.me> MFC after: 4 weeks
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#
ac4030b7 |
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20-Dec-2013 |
George V. Neville-Neil <gnn@FreeBSD.org> |
Add another Haswell model (0x45) to the set of supported chips. Model 0x45 appears, for example, in late 2013 Mac Book Pro models and is properly emulated by VMware.
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#
026346c8 |
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20-Dec-2013 |
Attilio Rao <attilio@FreeBSD.org> |
o Remove assertions on ipa_version as sometimes the version detection using cpuid can be quirky (this is the case of VMWare without the vPMC support) but fail to probe hwpmc. o Apply the fix for XEON family of processors as established by 315338-020 document (bug AJ85). Sponsored by: EMC / Isilon storage division Reviewed by: fabient
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#
1c12d03f |
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30-Apr-2013 |
Davide Italiano <davide@FreeBSD.org> |
Complete r250097: Do not change the initialization order in pmc_intel_initialize().
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#
e1bd42c2 |
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30-Apr-2013 |
Davide Italiano <davide@FreeBSD.org> |
When hwpmc(4) module is unloaded it reports a double leakage. This happens at least if FreeBSD is ran under VirtualBox. In order to avoid the leakage, properly deallocate structures in case CPU claims that hw performance monitoring counters are not supported. Reported by: hiren
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#
4b226201 |
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03-Apr-2013 |
Sean Bruno <sbruno@FreeBSD.org> |
Trailing whitespace cleanup along with 80 column enforcemnt. Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
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#
cc0c1555 |
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28-Mar-2013 |
Sean Bruno <sbruno@FreeBSD.org> |
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
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#
3f929d8c |
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31-Jan-2013 |
Sean Bruno <sbruno@FreeBSD.org> |
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
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#
fabe02f5 |
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19-Oct-2012 |
Sean Bruno <sbruno@FreeBSD.org> |
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */) Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
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#
1e862e5a |
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06-Sep-2012 |
Fabien Thomas <fabient@FreeBSD.org> |
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan
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#
f39e915e |
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17-Jun-2012 |
Davide Italiano <davide@FreeBSD.org> |
Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D). Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine. Approved by: gnn (mentor) MFC after: 3 days
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#
eecb732d |
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10-May-2012 |
Fabien Thomas <fabient@FreeBSD.org> |
Remove out of date KASSERT that fire with soft PMC. MFC after: 1 week
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#
f5f9340b |
|
28-Mar-2012 |
Fabien Thomas <fabient@FreeBSD.org> |
Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
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#
ef902782 |
|
27-Mar-2012 |
Oleksandr Tymoshenko <gonzo@FreeBSD.org> |
Fix crash on VirtualBox (and probably on some real hardware): - Do not cover error returned by pmc_core_initialize with the result of pmc_uncore_initialize, fail right away. - Give a user something to report instead failing silently Reported by: Alexandr Kovalenko <never@nevermind.kiev.ua>
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#
78d763a2 |
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01-Mar-2012 |
Davide Italiano <davide@FreeBSD.org> |
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
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#
a7d5f7eb |
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19-Oct-2010 |
Jamie Gritton <jamie@FreeBSD.org> |
A new jail(8) with a configuration file, to replace the work currently done by /etc/rc.d/jail.
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#
c8d050b5 |
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16-Apr-2010 |
Fabien Thomas <fabient@FreeBSD.org> |
MFC r206089, r206684: - Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
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#
1fa7f10b |
|
02-Apr-2010 |
Fabien Thomas <fabient@FreeBSD.org> |
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ
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#
68c3e041 |
|
18-Dec-2009 |
Joseph Koshy <jkoshy@FreeBSD.org> |
Recognize Intel CPUs with Family 0x6, Models 0x1E and 0x1F. Submitted by: Marc Unangst <mju at panasas dot com>
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#
597979c4 |
|
27-Jan-2009 |
Jeff Roberson <jeff@FreeBSD.org> |
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events. Reviewed by: jkoshy Sponsored by: Nokia
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#
b4d091f3 |
|
03-Dec-2008 |
Joseph Koshy <jkoshy@FreeBSD.org> |
Fixes for Core2 Extreme support. Submitted by: "Artem Belevich" <artemb at gmail dot com>
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#
0cfab8dd |
|
27-Nov-2008 |
Joseph Koshy <jkoshy@FreeBSD.org> |
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom). In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time. Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters. - Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events. Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished. - In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code. - Minor code tweaks: staticize a global, freshen a few comments. Tested by: gnn
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#
5113aa0a |
|
26-Nov-2008 |
Jung-uk Kim <jkim@FreeBSD.org> |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). Reviewed by: jhb, peter (early amd64 version)
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#
edfea6b4 |
|
15-Nov-2008 |
Joseph Koshy <jkoshy@FreeBSD.org> |
Fix assertions. Reported by: keramida
|
#
e829eb6d |
|
09-Nov-2008 |
Joseph Koshy <jkoshy@FreeBSD.org> |
- Separate PMC class dependent code from other kinds of machine dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question. Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations. - Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class. - Move code common to Intel CPUs to file "hwpmc_intel.c". - Move TSC handling to file "hwpmc_tsc.c".
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#
c5153e19 |
|
01-May-2005 |
Joseph Koshy <jkoshy@FreeBSD.org> |
Add convenience APIs pmc_width() and pmc_capabilities() to -lpmc. Have pmcstat(8) and pmccontrol(8) use these APIs. Return PMC class-related constants (PMC widths and capabilities) with the OP GETCPUINFO call leaving OP PMCINFO to return only the dynamic information associated with a PMC (i.e., whether enabled, owner pid, reload count etc.). Allow pmc_read() (i.e., OPS PMCRW) on active self-attached PMCs to get upto-date values from hardware since we can guarantee that the hardware is running the correct PMC at the time of the call. Bug fixes: - (x86 class processors) Fix a bug that prevented an RDPMC instruction from being recognized as permitted till after the attached process had context switched out and back in again after a pmc_start() call. Tighten the rules for using RDPMC class instructions: a GETMSR OP is now allowed only after an OP ATTACH has been done by the PMC's owner to itself. OP GETMSR is not allowed for PMCs that track descendants, for PMCs attached to processes other than their owner processes. - (P4/HTT processors only) Fix a bug that caused the MI and MD layers to get out of sync. Add a new MD operation 'get_config()' as part of this fix. - Allow multiple system-mode PMCs at the same row-index but on different CPUs to be allocated. - Reject allocation of an administratively disabled PMC. Misc. code cleanups and refactoring. Improve a few comments.
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#
7ad17ef9 |
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20-Apr-2005 |
Marcel Moolenaar <marcel@FreeBSD.org> |
Include <sys/pmc.h> instead of <machine/pmc_mdep.h>. The MI header includes the MD header for us. Do not include <machine/specialreg.h> as it is not a header file that can be included from MI files. It is included from <machine/pmc_mdep.h> if so needed and possible. Ok'd: jkoshy@
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#
ebccf1e3 |
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18-Apr-2005 |
Joseph Koshy <jkoshy@FreeBSD.org> |
Bring a working snapshot of hwpmc(4), its associated libraries, userland utilities and documentation into -CURRENT. Bump FreeBSD_version. Reviewed by: alc, jhb (kernel changes)
|