bhnd: Use rman_get_type in bhndb_find_resource_limits

Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D44126

sys: Remove $FreeBSD$: one-line .h pattern

Remove /^\s*\*+\s*\$FreeBSD\$.*$\n/

bhnd: clean up empty lines in .c and .h files

bhndb(4): Implement bridge support for the BCM4312 and other PCI_V0 chipsets.

Very early (PCI_V0) Broadcom PCI Wi-Fi chipsets have a few quirks when
compared to later PCI(e) core revisions:

- The standard static BAR0 mapping of the PCI core registers is discontiguous,
with siba's cfg0 register block mapped distinctly from the other core
registers.
- No dedicated ChipCommon register mapping is provided; instead, the
single configurable register window must be used to access both
ChipCommon and D11 core registers. The D11 core's operational semantics
guarantee the safety of -- after disabling interrupts -- borrowing
the single dynamic register window to perform the few ChipCommon
operations required by a driver.

To support these early PCI devices:

- Allow defining multiple discontiguous BHNDB_REGWIN_T_CORE register
windows that map a single port/region, and producing bridged resource
allocations backed by those discontiguous windows.
- Support stealing existing register window allocations to fulfill indirect
bhnd(4) bus I/O requests within address ranges tagged with
BHNDB_ALLOC_FULFILL_ON_OVERCOMMIT.
- Fix an inverted test of bhndb_is_pcie_attached() that disabled
PCI-only clock bring-up required by these devices.

Approved by: adrian (mentor, implicit)
Sponsored by: The FreeBSD Foundation

bhnd(4): implement MIPS and PCI(e) interrupt support

On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the
common bhnd(4) core drivers; we now register an INTRNG child PIC that
handles routing of backplane interrupt vectors via the MIPS core.

On BHND PCI devices, backplane interrupt vectors are now routed to the
PCI/PCIe host bridge core when bus_setup_intr() is called, where they are
dispatched by the PCI core via a host interrupt (e.g. INTx/MSI).

The bhndb(4) bridge driver tracks registered interrupt handlers for the
bridged bhnd(4) devices and manages backplane interrupt routing, while
delegating actual bus interrupt setup/teardown to the parent bus on behalf
of the bridged cores.

Approved by: adrian (mentor, implicit)
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D12518

bhnd: Add support for supplying bus I/O callbacks when initializing an EROM
parser.

This allows us to use the EROM parser API in cases where the standard bus
space I/O APIs are unsuitable. In particular, this will allow us to parse
the device enumeration table directly from bhndb(4) drivers, prior to
full attach and configuration of the bridge.

Approved by: adrian (mentor)
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D12510

Migrate bhndb(4) to the new bhnd_erom API.

Adds support for probing and initializing bhndb(4) bridge state using
the bhnd_erom API, ensuring that full bridge configuration is available
*prior* to actually attaching and enumerating the bhnd(4) child device,
allowing us to safely allocate bus-level agent/device resources during
bhnd(4) bus enumeration.

- Add a bhnd_erom_probe() method usable by bhndb(4). This is an analogue
to the existing bhnd_erom_probe_static() method, and allows the bhndb
bridge to discover the best available erom parser class prior to newbus
probing of its children.
- Add support for supplying identification hints when probing erom
devices. This is required on early EXTIF-only chipsets, where chip
identification registers are not available.
- Migrate bhndb over to the new bhnd_erom API, using bhnd_core_info
records rather than bridged bhnd(4) device_t references to determine
the bridged chipsets' capability/bridge configuration.
- The bhndb parent (e.g. if_bwn) is now required to supply a hardware
priority table to the bridge. The default table is currently sufficient
for our supported devices.
- Drop the two-pass attach approach we used for compatibility with bhndb(4) in
the bhnd(4) bus drivers, and instead perform bus enumeration immediately,
and allocate bridged per-child bus-level resources during that enumeration.

Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D7768

bhndb(4): Drop MIPS-incompatible __builtin_ctz dependency.

This replaces the bitfield representation of the bhndb register window
freelist with the bitstring API, eliminating a dependency on
(MIPS-unsupported) __builtin_ctz().

Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D7495

[bhnd] Add bhnd bridge support for bus_adjust_resource().

Adds support for adjusting active bus resource allocations, limiting the
range to the constraints of the register window within which the resource
is mapped.

This is the final set of bhnd changes required to support delegating
ChipCommon's register space to child devices.

Submitted by: Landon Fuller <landonf@landonf.org>
Differential Revision: https://reviews.freebsd.org/D6470

[bhnd] Add support for specifying the address space used by bhndb children

This adds support for specifying the address space used by a bridge child;
this will either be the bridged SoC address space, or the host address space
required by children that map non SoC-address ranges from the PCI BAR.

This is necessary to support SROM/OTP child devices that live directly
beneath the bhndb device and require access to host resources, instead
of the standard behavior of delegating access to the bridged SoC address
space.

Submitted by: Landon Fuller <landonf@landonf.org>
Differential Revision: https://reviews.freebsd.org/D5757

Bring over the initial rewrite of the broadcom bus support found in their
SoCs and various chips (including, famously, their wifi chips.)

This is "just" (all 20,000 lines of it) code to enumerate the various
versions of busses inside these devices, including the PCI bridge and
the direct SIBA bridge found in MIPS chips.

It also includes shared code for some bus operations (suspend, resume, etc);
EEPROM/SROM/etc parsing and other things that are shared between chips.

Eventually this'll replace the code that bwi/bwn uses for the internal
bus, as well as some apparently upcoming mips74k broadcom SoC support
which uses bwn!

Thanks to Landon Fuller <landonf@landonf.org> for all this work!

Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT