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178cf4b9 |
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19-Apr-2024 |
Gordon Bergling <gbe@FreeBSD.org> |
arm: Fix a typo in a KASSERT message - s/resoure/resource/ MFC after: 5 days
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#
685dc743 |
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16-Aug-2023 |
Warner Losh <imp@FreeBSD.org> |
sys: Remove $FreeBSD$: one-line .c pattern Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
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#
a0e20c0d |
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04-Aug-2023 |
Andrew Turner <andrew@FreeBSD.org> |
Limit the number of CPUs in the gicv1/2 driver The GICv2 can only send IPIs to 8 CPUs. Because of this it should only be in machines with no more than 8 cores. Create a new macro to hold this limit to reduce the size of the softc. Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D41322
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#
d7e3b05b |
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14-Dec-2022 |
Elliott Mitchell <ehem+freebsd@m5p.com> |
arm: remove passing trapframe to intr_ipi_dispatch() This was needed before INTRNG was in place and handling the push of curthread->td_intr_frame. Since INTRNG now handles this, there is no longer and need for playing around with the frame inside IPI interrupts.
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#
11d08e7e |
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22-Aug-2022 |
Bjoern A. Zeeb <bz@FreeBSD.org> |
arm/gic: fix a KASSERT in arm_gic_reserve_msi_range() Fix the off-by-one in the KASSERT in arm_gic_reserve_msi_range() allowing the MSIs being allocated at the end of the IRQ range. Reported by: bz Submitted by: andrew Reviewed by: andrew MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D36291
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#
258958b3 |
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05-Jul-2022 |
Mitchell Horne <mhorne@FreeBSD.org> |
ddb: use _FLAGS command macros where appropriate Some command definitions were forced to use DB_FUNC in order to specify their required flags, CS_OWN or CS_MORE. Use the new macros to simplify these. Reviewed by: markj, jhb MFC after: 3 days Sponsored by: Juniper Networks, Inc. Sponsored by: Klara, Inc. Differential Revision: https://reviews.freebsd.org/D35582
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#
904a1375 |
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10-Mar-2022 |
John Baldwin <jhb@FreeBSD.org> |
ddb: Add 'show gic <name>' and 'show all gics' commands. To handle the different register layouts for different versions, add a GIC_DB_SHOW() method. Currently this hook is only implemented for versions 1 and 2. Sponsored by: University of Cambridge, Google, Inc. Differential Revision: https://reviews.freebsd.org/D34415
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#
36499dc7 |
|
09-Dec-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Fix a set but not used warning in the arm GIC driver Sponsored by: Innovate UK
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#
18c21394 |
|
29-Sep-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Add a gic interface to allocate MSI interrupts The previous update to handle the gicv2m as a child of the gicv3 driver assumed there was only a single gicv2m child. On some hardware there are multiple children. Support this by removing the mbi ivars and adding a new interface to handle MSI allocation in a given range. Tested by: mw, trasz Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D32224
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#
f3aa0098 |
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27-Sep-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Use mtx_lock_spin in the gic driver The mutex was changed to a spin lock when the MSI/MSI-X handling was moved from the gicv2m to the gic driver. Update the calls to lock and unlock the mutex to the spin variant. Submitted by: jrtc27 ("Change all the mtx_(un)lock(&sc->mutex) to be the _spin versions.") Reported by: mw, antranigv@freebsd.am Sponsored by: The FreeBSD Foundation
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#
90f33f34 |
|
14-Sep-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Remove a bogus assertion from the gic drivers When setting a message based interrupt range we set the base and count. In an earlier the count was implemented as an end value, however the asserts used to check this value was correct were incorrectly left in. Reported by: emaste Sponsored by: The FreeBSD Foundation
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#
c6f3076d |
|
01-Sep-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Move the GICv2m msi handling to the parent This is in preperation for adding support for the GICv2m driver as a child of the GICv3 driver. PR: 258136 Reported by: trasz Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31767
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#
dd6c1c2a |
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25-Jan-2021 |
Andrew Turner <andrew@FreeBSD.org> |
Remove redundantcy from the arm GIC softc A struct recource already contains the bus_space_tag_t and bus_space_handle_t. There is no neec to read them and store them again in the drivers softc. Remove them and use the struct resource directly with bus_read_* and bus_write_*. Reviewed by: mmel Differential Revision: https://reviews.freebsd.org/D28339
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#
65454883 |
|
01-Sep-2020 |
Mateusz Guzik <mjg@FreeBSD.org> |
arm: clean up empty lines in .c and .h files
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#
ddb74373 |
|
06-Sep-2018 |
Andrew Turner <andrew@FreeBSD.org> |
Remove the check that the Arm generic interrupt controller variant is non-zero. This is the case on qemu, so remove it to allow us to boot there. This change is needed to boot on qemu with ACPI. Approved by: re (gjb)
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#
011dc75d |
|
30-Jul-2018 |
Andrew Turner <andrew@FreeBSD.org> |
Remove teh non-INTRNG code from the ARM GIC interrupt controller driver. We don't build for the non-INTRNG case and it was makeing the code harder to read.
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#
6cd04bcd |
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24-Feb-2018 |
Olivier Houchard <cognet@FreeBSD.org> |
Use NULL as a mtx type instead of "", as it otherwise confuses WITNESS.
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#
ee42eb7e |
|
11-Jan-2018 |
Andrew Turner <andrew@FreeBSD.org> |
iAdd ACPI attachments the the GIC and GICv3 interrupt controller drivers. For each we need to walk the MADT to find which we have, then add the driver as needed. As each may have a child they will each walk the same table to find these details. Reviewed by: mmel Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D8720
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151ba793 |
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24-Dec-2017 |
Alexander Kabaev <kan@FreeBSD.org> |
Do pass removing some write-only variables from the kernel. This reduces noise when kernel is compiled by newer GCC versions, such as one used by external toolchain ports. Reviewed by: kib, andrew(sys/arm and sys/arm64), emaste(partial), erj(partial) Reviewed by: jhb (sys/dev/pci/* sys/kern/vfs_aio.c and sys/kern/kern_synch.c) Differential Revision: https://reviews.freebsd.org/D10385
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#
af3dc4a7 |
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27-Nov-2017 |
Pedro F. Giffuni <pfg@FreeBSD.org> |
sys/arm: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
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#
c33f3f1e |
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03-Jul-2017 |
Emmanuel Vadot <manu@FreeBSD.org> |
arm: gic: Change GIC_DEBUG_SPURIOUS to TUNABLE On armv6 default to 1 if INVARIANTS is set On arm64 always default to 0 Discussed with: andrew, ian, mmel
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#
7db267b3 |
|
26-Jun-2017 |
Oleksandr Tymoshenko <gonzo@FreeBSD.org> |
[arm] Use correct index value when checking range validity Reviewed by: andrew MFC after: 3 weeks Differential Revision: https://reviews.freebsd.org/D9145
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#
899a3629 |
|
25-Apr-2017 |
Olivier Houchard <cognet@FreeBSD.org> |
In arm_gicv2m_alloc_msi(), if we found a suitable irq range, leave the loop before we increase irq again, or we'd end up choosing an irq, and then really using the next one, even if it's not available. Also in the inner loop, correct the end check so that we check every irq, even the last one. This makes the msk(4) adapter able to use MSI on Softiron Overdrive 1000.
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11011dfc |
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13-Apr-2017 |
Alexander Kabaev <kan@FreeBSD.org> |
Use proper fields to check for interrupt trigger mode.
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#
3ce73b26 |
|
12-Dec-2016 |
Jayachandran C. <jchandra@FreeBSD.org> |
Fix gic_cpu_mask() calculation in ARM GIC r309616 changed the definition of GICD_ITARGETSR(n) to take the irq id as argument, but the usage of the macro in gic_cpu_mask() was not updated to reflect this. This causes the cpu mask to be computed incorrectly. Update the GICD_ITARGETSR() call to fix this, this fixes a hang seen while booting freebsd on qemu-system-aarch64 with SMP enabled.
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#
be04b41d |
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06-Dec-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Create two GIC ivars to find the bus type and GIC hardware version. These will be used by the gicv2m and ITS ACPI drivers to only attach to the correct parent. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
c417fba9 |
|
06-Dec-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Move the common bit manipulation macros from the GICv3 header to the common GIC header file. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
4d7d72fb |
|
05-Dec-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Adda new common GIC header to handle the common parts of the GICv2 and GICv3 drivers. For now it just contains common distributor registers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
59202261 |
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30-Nov-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Only include FDT headders when building for FDT. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
df767535 |
|
14-Nov-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Stop including fdt_common.h from the arm code when it's unneeded. Sponsored by: ABT Systems Ltd
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#
87acb7f8 |
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11-Nov-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Use the modern spelling of ofw_bus_node_is_compatible in sys/arm. Sponsored by: ABT Systems Ltd
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#
0c5434ae |
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26-Oct-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Pull the common FDT interrupt values into a new header rather than be magic numbers. Sponsored by: DARPA, AFRL
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#
6dcc1178 |
|
08-Oct-2016 |
Oleksandr Tymoshenko <gonzo@FreeBSD.org> |
Fix release MSI method for ARM GIC
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#
0f9f4091 |
|
20-Sep-2016 |
Wojciech Macek <wma@FreeBSD.org> |
Add support for SPI-mapped MSI interrupts outside of GICv2m. SPI-mapped MSI interrupts coming from a controller other than GICv2m need to have their trigger and polarity properly configured. This patch fixes MSI/MSI-X on Annapurna Alpine platform with GICv2. Obtained from: Semihalf Submitted by: Michal Stanek <mst@semihalf.com> Sponsored by: Annapurna Labs Reviewed by: skra, wma Differential Revision: https://reviews.freebsd.org/D7698
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#
727c18a8 |
|
01-Aug-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Split out the FDT parts of the GICv2 interrupt controller driver. This will allow us to add an ACPI attachment for arm64. Obtained from: ABT Systems Ltd MFC after: 1 month Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D7307
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#
477ef5ca |
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03-Jun-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
Define irq variable only in the block where used.
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#
02a1932d |
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31-May-2016 |
Andrew Turner <andrew@FreeBSD.org> |
arm_gic_map is a mask not the CPUs ID, there is no need to shift it. Pointy-hat to: andrew Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
9a53d57e |
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31-May-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Bin interrupts to the correct CPU when we boot on a non-zero CPU. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
74bf4975 |
|
29-May-2016 |
Michal Meloun <mmel@FreeBSD.org> |
ARM GIC: Allow to setup interrupt without configuration data. In some cases, like for PCI devices, only interrupt numbers are enumerated from HW. In this case, use INTR_foo_CONFORM as level and trigger values.
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#
9346e913 |
|
18-May-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Return the struct intr_pic pointer from intr_pic_register. This will be needed in later changes where we may not be able to lock the pic list lock to perform a lookup, e.g. from within interrupt context. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
1f420ed4 |
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17-May-2016 |
Bjoern A. Zeeb <bz@FreeBSD.org> |
The GIC (v2 at least) has a bit in the TYPER register to indicate whether the GIC supports the Security Extensions or not. This bit is not the same as the CPU one. Currently we are not checking for either before trying to write to the special registers. This can lead to problems on hardware or simulators that do not provide the security extensions. Add the missing checks. Their interactions with the CPU flag is not entirely clear to me but using a macro will make it easier to quickly adjust the condition once the CPU bits are sorted as well. Reviewed by: br Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D6397
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3fc155dc |
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16-May-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Introduce MSI and MSI-X support to intrng. This adds a new msi device interface with 5 methods to mirror the 5 MSI/MSI-X methods in the pcib interface. The pcib driver will need to perform a device specific lookup to find the MSI controller and pass this to intrng as the xref. Intrng will finally find the controller and have it handle the requested operation. Obtained from: ABT Systems Ltd MFH: yes Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D5985
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#
cd642c88 |
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05-May-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
INTRNG - redefine struct intr_map_data to avoid headers pollution. Each struct associated with some type defined in enum intr_map_data_type must have struct intr_map_data on the top of its own definition now. When such structs are used, correct type and size must be filled in. There are three such structs defined in sys/intr.h now. Their definitions should be moved to corresponding headers by follow-up commits. While this change was propagated to all INTRNG like PICs, pic_map_intr() method implementations were corrected on some places. For this specific method, it's ensured by a caller that the 'data' argument passed to this method is never NULL. Also, the return error values were standardized there.
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#
255eff3b |
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04-May-2016 |
Pedro F. Giffuni <pfg@FreeBSD.org> |
sys/arm: Minor spelling fixes. Only affects comments: no functional change.
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#
6138946f |
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21-Apr-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Make the GIC SGI global variables static, they are only ever used within within this file. Approved by: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
59c3cb81 |
|
15-Apr-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine independent code that needs to know about INTRNG such as PCI drivers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
2049b03c |
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15-Apr-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Add a flag field to struct gic_irqsrc and use it to mark when we should write to the End of Interrupt (EOI) register before handling the interrupt. This should be a noop as it will be set for all edge triggered interrupts, however this will not be the case for MSI interrupts. These are also edge triggered, however we should not write to the EOI register until later in arm_gic_pre_ithread. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
e2d4ce8a |
|
15-Apr-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Add initial GICv2m support to the arm GIC driver. This will be used to support MSI and MSI-X interrupts, however intrng needs updates before this can happen. For now we just attach the driver until the MSI API is ready. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D5950
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#
f46a4878 |
|
07-Apr-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
Properly initialize isrc_cpu field of ISRC which is setup for an IPI.
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#
5b613c19 |
|
07-Apr-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
Implement intr_isrc_init_on_cpu() and use it to replace very same code implemented in every interrupt controller driver running SMP. This function returns true, if provided ISRC should be enabled on given cpu.
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#
53b832b0 |
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04-Apr-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Add a table to map from the FreeBSD CPUID space to the GIC CPUID space. On many SoCs these two are the same, however there is no requirement for this to be the case, e.g. on the ARM Juno we boot on what the GIC thinks of as CPU 2, but FreeBSD numbers it CPU 0. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
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#
bff6be3e |
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04-Apr-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
Remove FDT specific parts from INTRNG. Change its interface to make it universal. (1) New struct intr_map_data is defined as a container for arbitrary description of an interrupt used by a device. Typically, an interrupt number and configuration relevant to an interrupt controller is encoded in such description. However, any additional information may be encoded too like a set of cpus on which an interrupt should be enabled or vendor specific data needed for setup of an interrupt in controller. The struct intr_map_data itself is meant to be opaque for INTRNG. (2) An intr_map_irq() function is created which takes an interrupt controller identification and struct intr_map_data as arguments and returns global interrupt number which identifies an interrupt. (3) A set of functions to be used by bus drivers is created as well as a corresponding set of methods for interrupt controller drivers. These sets take both struct resource and struct intr_map_data as one of the arguments. There is a goal to keep struct intr_map_data in struct resource, however, this way a final solution is not limited to that. (4) Other small changes are done to reflect new situation. This is only first step aiming to create stable interface for interrupt controller drivers. Thus, some temporary solution is taken. Interrupt descriptions for devices are stored in INTRNG and two specific mapping function are created to be temporary used by bus drivers. That's why the struct intr_map_data is not opaque for INTRNG now. This temporary solution will be replaced by final one in next step. Differential Revision: https://reviews.freebsd.org/D5730
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#
6c5b1ed4 |
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29-Mar-2016 |
Andrew Turner <andrew@FreeBSD.org> |
Read the CPU ID for the current CPU from the GIC. The GIC may have a different ID space than the kernel. Because of this we need to read the ID from the hardware. The hardware will provide this value to the CPU by reading any of the first 8 Interrupt Processor Targets Registers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D5706
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#
61c8fde5 |
|
24-Mar-2016 |
Svatopluk Kraus <skra@FreeBSD.org> |
Generalize IPI support for ARM intrng and use it for interrupt controller IPI provider. New struct intr_ipi is defined which keeps all info about an IPI: its name, counter, send and dispatch methods. Generic intr_ipi_setup(), intr_ipi_send() and intr_ipi_dispatch() functions are implemented. An IPI provider must implement two functions: (1) an intr_ipi_send_t function which is able to send an IPI, (2) a setup function which initializes itself for an IPI and calls intr_ipi_setup() with appropriate arguments. Differential Revision: https://reviews.freebsd.org/D5700
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#
64f7e6ae |
|
14-Mar-2016 |
Wojciech Macek <wma@FreeBSD.org> |
Fix GIC interrupt decoding in INTRNG code Bug was already fixed in not-INTRNG code, it needs to be corrected here as well. Source: https://reviews.freebsd.org/rS294422 Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: cognet, wma Approved by: cognet (mentor) Differential Revision: https://reviews.freebsd.org/D5029
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#
90c1c677 |
|
20-Jan-2016 |
Zbigniew Bodek <zbb@FreeBSD.org> |
Fix GIC FDT interrupts decoding Interrupt type in FDT was interpreted incorrectly. Patch taken from freebsd-arm thread 'GIC - interrupts interpretation in DTS/FDT': https://lists.freebsd.org/pipermail/freebsd-arm/2015-August/012145.html Reviewed by: ian, imp Obtained from: Semihalf Sponsored by: Stormshield Submitted by: Michal Stanek <mst@semihalf.com> Differential revision: https://reviews.freebsd.org/D4215
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#
2b3ad188 |
|
17-Dec-2015 |
Adrian Chadd <adrian@FreeBSD.org> |
[intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c. The ci20 port (by kan@) is going to reuse almost all of the intrng code since the SoC in question looks suspiciously like someone took an ARM SoC design and replaced the ARM core with a MIPS core. * migrate out the code; * rename ARM_ -> INTR_; * rename arm_ -> intr_; * move the interrupt flush routine from intr.c / intrng.c into arm/machdep_intr.c - removing the code duplication and removing the ARM specific bits from here. Thanks to the Star Wars: The Force Awakens premiere line for allowing me a couple hours of quiet time to finish the universe builds. Tested: * make universe TODO: * The structure definitions in subr_intr.c still includes machine/intr.h which requires one duplicates all of the intrng definitions in the platform code (which kan has done, and I think we don't have to.) Instead I should break out the generic things (function declarations, common intr structures, etc) into a separate header. * Kan has requested I make the PIC based IPI stuff optional.
|
#
ab1910e8 |
|
02-Dec-2015 |
Michal Meloun <mmel@FreeBSD.org> |
ARM: Fix of detection of root interrupt controller. This fixes detection of root interrupt controller for cases, when interrupt parent is not defined at all or it's not defined directly in controller node. Approved by: kib (mentor)
|
#
20fc8f2b |
|
27-Nov-2015 |
Michal Meloun <mmel@FreeBSD.org> |
ARM: Cumulative fixes for GIC - fix detection of interrupt root controller - allow (but warn) unsupported configuration bits - dont send EOI for spurious interrupts - print more informations for spurious interrupts - use device_printf() where appropriate Reviewed by: ian (earlier version) Approved by: kib (mentor)
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#
7b19ce31 |
|
21-Oct-2015 |
Ian Lepore <ian@FreeBSD.org> |
Move arm_gic_bind() out of the #ifdef SMP block to fix compile errors in the not-SMP case. This is safe because arm_irq_next_cpu() will return the cpuid of the current/only core in the not-SMP case. Submitted by: Bartosz Szczepanek @ semihalf
|
#
d8917694 |
|
20-Oct-2015 |
Ian Lepore <ian@FreeBSD.org> |
Uncomment some rather important code that was commented out for benchmarking. Normally this routine is supposed to loop until the PIC returns a "no more interrupts pending" indication. I had commented that out to do just one interrupt per invokation to do some timing tests. Spotted by: Svata Kraus Pointy Hat: ian
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#
26b9f0eb |
|
18-Oct-2015 |
Ian Lepore <ian@FreeBSD.org> |
Only decode fdt data which belongs to the GIC controller. The interrupts-extended property is a list of controller-specific interrupt tuples for more than one controller. The decode routine of every PIC gets called in the pre-INTRNG code (nexus doesn't know which device instance belongs to which fdt node), so the GIC code has to check each FDT node it is asked to decode to ensure it is the owner. Because in the pre-INTRNG world there can only be one instance of a GIC, it's safe to cache the results of a positive lookup in a static variable to avoid the expensive lookups on subsequent calls. Submitted by: Svatopluk Kraus <onwahe@gmail.com> Differential Revision: https://reviews.freebsd.org/D2345
|
#
686450c8 |
|
18-Oct-2015 |
Ian Lepore <ian@FreeBSD.org> |
Import ARM_INTRNG, the "next generation" interrupt architecture for arm and armv6 architecures. The primary enhancement over the old design is support for hierarchical interrupt controllers (such as a gpio driver which can receive interrupts from a root PIC and act as a PIC itself for clients interested in handling a change of gpio pin state as an interrupt). The new code also provides an infrastructure for mapping interrupts described in metadata in the form of a "controller reference plus interrupt number" tuple into the simple "0-n" flat numeric space understood by rman and the bus resource mechanisms. Use of the new code is enabled by setting the ARM_INTRNG option, and by making a few simple changes to the platform's support code. In addition each existing PIC driver needs changes to be ready for INTRNG; this commit contains the changes for the arm/gic driver, which most armv6 SoCs use, but it does not enable the new code yet on any platform. This project has been many years in the making, starting as a GSoC project by Jakub Klama (jceel@) in 2012. That didn't get committed right away and the source base evolved out from under it to some degree. In 2014 I rebased the diffs to then -current and did some enhancements in the area of mapping interrupt numbers and storing associated fdt data, then the project went cold again for a while. Eventually Svata Kraus took that work in progress and did another big round of work on it, removing most of the remaining rough edges. Finally I took that and made one more pass through it, mostly disabling the "INTR_SOLO" feature for now, pending further design discussions on how to most efficiently dispatch a pending interrupt through more than one layer of PIC. The current code with the INTR_SOLO feature disabled uses approximate 100 extra cpu cycles for each cascaded PIC the interrupt has to be passed to, so what's left to do is about efficiency, not correct operation. Differential Revision: https://reviews.freebsd.org/D2047
|
#
7ce00ee7 |
|
18-Oct-2015 |
Ian Lepore <ian@FreeBSD.org> |
Rename arm_init_secondary_ic() -> arm_pic_init_secondary(). The latter is the name the function will have when the new ARM_INTRNG code is integrated, and doing this rename first will make it easier to toggle the new interrupt handling code on/off with a config option for debugging.
|
#
66fb2f18 |
|
23-May-2015 |
Andrew Turner <andrew@FreeBSD.org> |
Remove trailing whitespace from sys/arm/arm
|
#
562246df |
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31-Mar-2015 |
Ganbold Tsagaankhuu <ganbold@FreeBSD.org> |
Add necessary changes to support various Amlogic SoC devices specially aml8726-m6 and aml8726-m8b SoC based devices. aml8726-m6 SoC exist in devices such as Visson ATV-102. Hardkernel ODROID-C1 board has aml8726-m8b SoC. The following support is included: Basic machdep code SMP Interrupt controller Clock control driver (aka gate) Pinctrl Timer Real time clock UART GPIO I2C SD controller SDXC controller USB Watchdog Random number generator PLL / Clock frequency measurement Frame buffer Submitted by: John Wehle Approved by: stas (mentor)
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b63ea394 |
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23-Feb-2015 |
Zbigniew Bodek <zbb@FreeBSD.org> |
Fix endianness on FDT read in ARM GIC Submitted by: Jakub Palider <jpa@semihalf.com> Reviewed by: ian, nwhitehorn Obtained from: Semihalf
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3f53a2d6 |
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11-Jan-2015 |
Andrew Turner <andrew@FreeBSD.org> |
Rename gic_init_secondary to arm_init_secondary_ic to help with the merge of the arm_intrng project branch.
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c9ac548c |
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11-Jan-2015 |
Andrew Turner <andrew@FreeBSD.org> |
Rework the GIC driver to ease the import of the arm_intrng branch. The common code has been pulled out to static functions.
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ed600fa7 |
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24-Dec-2014 |
Andrew Turner <andrew@FreeBSD.org> |
Rename pic_ipi_get to pic_ipi_read for intrng.
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d0e17309 |
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21-Dec-2014 |
Andrew Turner <andrew@FreeBSD.org> |
Further reduce the diff between the arm_intrng gic driver and the version in head.
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2fe8c9e1 |
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21-Dec-2014 |
Andrew Turner <andrew@FreeBSD.org> |
Reduce the diff to the arm_intrng project branch by having the read/write macros take the softc they are accessing.
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8971dd56 |
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13-Nov-2014 |
Zbigniew Bodek <zbb@FreeBSD.org> |
Fix typo in ARM GIC device_printf() Obtained from: Semihalf Sponsored by: The FreeBSD Foundation
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7cb146ae |
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15-Sep-2014 |
Ian Lepore <ian@FreeBSD.org> |
The private peripheral interrupts start at offset 16, not 0. Also, use names rather than inline mystery constants for these offsets. Pointed out by: andrew
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0e390441 |
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14-Sep-2014 |
Ian Lepore <ian@FreeBSD.org> |
Add a common routine for parsing FDT data describing an ARM GIC interrupt. In the fdt data we've written for ourselves, the interrupt properties for GIC interrupts have just been a bare interrupt number. In standard data that conforms to the published bindings, GIC interrupt properties contain 3-tuples that describe the interrupt as shared vs private, the interrupt number within the shared/private address space, and configuration info such as level vs edge triggered. The new gic_decode_fdt() function parses both types of data, based on the #interrupt-cells property. Previously, each platform implemented a decode routine and put a pointer to it into fdt_pic_table. Now they can just list this function in their table instead if they use arm/gic.c.
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4a396d7a |
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14-Sep-2014 |
Ian Lepore <ian@FreeBSD.org> |
Add compat strings for all the flavors of GIC this driver should support. Also allow the driver to attach to ofwbus as well as simplebus, some FDT data puts the root interrupt controller on the root bus.
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5e5c1724 |
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05-Sep-2014 |
Andrew Turner <andrew@FreeBSD.org> |
Add the virtual timer irq to the list of interrupts we enable on secondary cores.
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333b6dce |
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05-Aug-2014 |
Ian Lepore <ian@FreeBSD.org> |
Attach arm generic interrupt and timer drivers in the middle of BUS_PASS_INTERRUPT and BUS_PASS_TIMER, respectively.
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f0687d36 |
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12-Jun-2014 |
Ruslan Bukin <br@FreeBSD.org> |
Activate IRQ 30 (non-secure private timer IRQ) for case we are running in non-secure state.
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11d47032 |
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24-May-2014 |
Ian Lepore <ian@FreeBSD.org> |
Eliminate one of the causes of spurious interrupts on armv6. The arm weak memory ordering model allows writes to different devices to complete out of order, leading to a situation where the write that clears an interrupt source at a device can complete after a write that unmasks and EOIs the interrupt at the interrupt controller, leading to a spurious re-interrupt. This adds a generic barrier function specific to the needs of interrupt controllers, and calls that function from the GIC and TI AINTC controllers. There may still be other soc-specific controllers that need to make the call. Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com> MFC after: 3 days
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add35ed5 |
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02-Feb-2014 |
Ian Lepore <ian@FreeBSD.org> |
Follow r261352 by updating all drivers which are children of simplebus to check the status property in their probe routines. Simplebus used to only instantiate its children whose status="okay" but that was improper behavior, fixed in r261352. Now that it doesn't check anymore and probes all its children; the children all have to do the check because really only the children know how to properly interpret their status property strings. Right now all existing drivers only understand "okay" versus something- that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
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4acd62c5 |
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01-Jan-2014 |
Zbigniew Bodek <zbb@FreeBSD.org> |
Add polarity and level support to ARM GIC Add suport for setting triggering level and polarity in GIC. New function pointer was added to nexus which corresponds to the function which sets level/sense in the hardware (GIC). Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf
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425a5c79 |
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30-Oct-2013 |
Ian Lepore <ian@FreeBSD.org> |
Do not EOI an interrupt until the point after the filter handlers / before threaded handlers. It's not easy to see from the diffs of this change exactly how it accomplishes the above. The arm_mask_irq() and arm_unmask_irq() functions are, respectively, the pre_thread and post_thread hooks. Not seen in these diffs, the arm_post_filter() routine also EOIs. The post_filter routine runs after filter handlers if there will be no threaded handlers, so it just EOIs. The pre_thread routine masks the interrupt (at the controller, not the source) and EOIs. So one way or another, the EOI happens at the point where filter handlers are done.
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cca928b9 |
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02-Aug-2013 |
Olivier Houchard <cognet@FreeBSD.org> |
Only receive the interrupts on the first core, to avoid duplicate interrupts.
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0f10ca6f |
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28-Jun-2013 |
Aleksandr Rybalko <ray@FreeBSD.org> |
o Initialize interrupt groups as Group 0 (secure interrupts). o Minor cleanup. Submitted by: Ruslan Bukin <br@bsdpad.com>
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10443bc3 |
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22-Apr-2013 |
Damjan Marion <dmarion@FreeBSD.org> |
Initialize GIC_PMRR register on ARM GIC. Provided by: Thomas Skibo
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cf1a573f |
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14-Aug-2012 |
Oleksandr Tymoshenko <gonzo@FreeBSD.org> |
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
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