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230687 |
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28-Jan-2012 |
marius |
MFC: r225931, r225932, r227000
Make sparc64 compatible with NEW_PCIB and enable it: - Implement bus_adjust_resource() methods as far as necessary and in non-PCI bridge drivers as far as feasible without rototilling them. - As NEW_PCIB does a layering violation by activating resources at layers above pci(4) without previously bubbling up their allocation there, move the assignment of bus tags and handles from the bus_alloc_resource() to the bus_activate_resource() methods like at least the other NEW_PCIB enabled architectures do. This is somewhat unfortunate as previously sparc64 (ab)used resource activation to indicate whether SYS_RES_MEMORY resources should be mapped into KVA, which is only necessary if their going to be accessed via the pointer returned from rman_get_virtual() but not for bus_space(9) as the later always uses physical access on sparc64. Besides wasting KVA if we always map in SYS_RES_MEMORY resources, a driver also may deliberately not map them in if the firmware already has done so, possibly in a special way. So in order to still allow a driver to decide whether a SYS_RES_MEMORY resource should be mapped into KVA we let it indicate that by calling bus_space_map(9) with BUS_SPACE_MAP_LINEAR as actually documented in the bus_space(9) page. This is implemented by allocating a separate bus tag per SYS_RES_MEMORY resource and passing the resource via the previously unused bus tag cookie so we later on can call rman_set_virtual() in sparc64_bus_mem_map(). As a side effect this now also allows to actually indicate that a SYS_RES_MEMORY resource should be mapped in as cacheable and/or read-only via BUS_SPACE_MAP_CACHEABLE and BUS_SPACE_MAP_READONLY respectively. - Do some minor cleanup like taking advantage of rman_init_from_resource(), factor out the common part of bus tag allocation into a newly added sparc64_alloc_bus_tag(), hook up some missing newbus methods and replace some homegrown versions with the generic counterparts etc. - While at it, let apb_attach() (which can't use the generic NEW_PCIB code as APB bridges just don't have the base and limit registers implemented) regarding the config space registers cached in pcib_softc and the SYSCTL reporting nodes set up.
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201052 |
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27-Dec-2009 |
marius |
Add a driver for the `Fire' JBus to PCIe bridges found in at least the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also already includes all the code to support the `Oberon' Uranus to PCIe bridges found in the Fujitsu-Siemens based Mx000 machines but due to lack of access to such a system for testing, probing of these bridges is currently disabled. Unfortunately, the event queue mechanism of these bridges for MSIs/ MSI-Xs matches our current MD and MI interrupt frameworks like square pegs fit into round holes so for now we are generous and use one event queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge (we use one event queue for the PCIe error messages). This seems tolerable as long as most devices just use one MSI/MSI-X anyway. Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should allow us to decouple the 1:1 mapping at the cost of no longer being able to bind MSIs/MSI-Xs to specific CPUs as we currently have no reliable way to quiesce a device during the transition of its MSIs/ MSI-Xs to another event queue. This would still require the problem of interrupt storms generated by devices which have no one-shot behavior or can't/don't mask interrupts while the filter/handler is executed (like the older PCIe NICs supported by bge(4)) to be solved though.
Committed from: 26C3
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