Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head to stable/9 as part of 9.0-RELEASE release cycle.

Approved by: re (implicit)

Remove duplicate header includes

- dump_avail layout should be sequence of [start, end)
pairs, not <start, size>.

Spotted by: alc@

- Populate dump_avail with proper values from phys_avail

Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
with the meaning of IM bits in the status register.

Reviewed by: jmallett, jchandra

uint64_t is 'unsigned long' in n64 build, so compiler is unhappy if the
format specifier in printf is "%llu".

Use "%ju" instead.

Fix a race between clock_intr() and tick_ticker() when updating
'counter_upper' and 'counter_lower_last'. The race exists because
interrupts are enabled even though tick_ticker() executes in a
critical section.

Fix a bug in clock_intr() in how it updates the cached values of
'counter_upper' and 'counter_lower_last'. They are updated only
when the COUNT register rolls over. More interestingly it will *never*
update the cached values if 'counter_lower_last' happens to be zero.

Get rid of superfluous critical section in clock_intr(). There is no
reason to do this because clock_intr() executes in hard interrupt
context.

Switch back to using 'tick_ticker()' as the cpu ticker for Sibyte.

Reviewed by: jmallett, mav

Remove redunant machine/cpuregs.h include.
Also, spell things like in machine/cpuregs.h instead of machine/cpu.h.

Fix Sibyte SMP kernel breakage caused by r208249.

We need to include the header file that provides declaration of the
smp_topo_none() function.

Adds JC's cleanup patches that fix it so
we call an platform dependant topo function as
well as clean up all the XLR specific ifdefs around
smp platform init.

Obtained from: JC

o) Remove default MAXMEM on SWARM; pmap can readily use lmem for >512M
physical addresses.
o) Set a local maxmem in sb_machdep.c to avoid trying to use pages over 2^64
under 32-bit ABIs. Our pmap needs corrected to use vm_paddr_t consistently,
then we can make vm_paddr_t 64-bit under 32-bit ABIs and add code in pmap
to limit phys_avail by the maximum PFN that a 32-bit PTE can hold.

Sibyte provides a 64-bit read-only counter that counts at half the processor
frequency. This counter can be accessed coherently from both cores.

Use this as the preferred timecounter for the SWARM kernels.

The CP0 COUNT register is unusable as the timecounter on SMP platforms because
the COUNT registers on different CPUs are not guaranteed to be in sync.

Add support for CPUs with cache coherent DMA. The two main changes are:

- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp

SMP support for the mips port.

The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.

Reviewed by: imp, rrs

Initialize interrupt controller early on.

Install the XTLB exception handler for Sibyte processors.

This is a workaround for the fact that the CFE is compiled as a 64-bit
application and therefore sets the SR_KX bit every time we call into
it (for e.g. console).

A TLB miss for any address above 0xc0000000 with the SR_KX bit set will
end up at the XTLB exception vector. We workaround this by copying the
standard TLB handler at the XTLB exception vector.

Approved by: imp (mentor)

- Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
it's not neccessary and might destroy data pased by trampoline or
boot loader

Remove Sibyte specific code from locore.S that sets the k0seg coherency.

Move it to platform_start() instead.

Approved by: imp (mentor)

Merge from projects/mips to head by hand:

Copy the files for the sibyte support (except files in sys/conf and
sys/mips/conf). This targets the Broadcom SWARM board (bcm91250) and
the SB-1 core in the BCM1250 SoC. This work was done by Neel Natu.

Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.

Centralize initialization of pcpu, and set curthread early...

Remove all CFE-specific code from locore.S. The CFE entrypoint initialization
is now done in platform-specific code.

Approved by: imp (mentor)

With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)

Add sibyte device support.

Submitted by: Neelkanth Natu