Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head to stable/9 as part of 9.0-RELEASE release cycle.

Approved by: re (implicit)

The FA526 belongs to the ARM9TDMI family

Add support for FA626TE.
Tested on GM8181 development board.

Let detailed info about CPU features print on Marvell Sheeva CPU as well.

Provide missing entry in the cpu_classes[].

Reported by: Maks Verver
MFC after: 1 week

Show the cpu info for fa526

Submitted by: Yohanes Nugroho <yohanes at gmail dot com>

Promote the cpu_class local variable to global and expose it in md_var.h

Reviewed by: freebsd-arm

Merge support for Gateworks Cambria boards:
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support

Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD

Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp

Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.

They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from: Marvell, Semihalf

The VM system no longer uses setPQL2(). Remove it and its helpers.

Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.

Obtained from: NetBSD

Say if the L2 cache is enabled or disabled as well.

Approved by: re (blanket)

elaborate on stepping names; add intel terminology to help
people cross-referencing intel docs

Reviewed by: imp, cognet
MFC after: 1 month

Identify the xscale 81342.

Finally bring it support for the i80219 XScale processor.

Submitted by: Max M. Boyarov <m.boyarov bsd by>

MFp4: Small cleanup of cpu messages at boot.

MI changes:
- provide an interface (macros) to the page coloring part of the VM system,
this allows to try different coloring algorithms without the need to
touch every file [1]
- make the page queue tuning values readable: sysctl vm.stats.pagequeue
- autotuning of the page coloring values based upon the cache size instead
of options in the kernel config (disabling of the page coloring as a
kernel option is still possible)

MD changes:
- detection of the cache size: only IA32 and AMD64 (untested) contains
cache size detection code, every other arch just comes with a dummy
function (this results in the use of default values like it was the
case without the autotuning of the page coloring)
- print some more info on Intel CPU's (like we do on AMD and Transmeta
CPU's)

Note to AMD owners (IA32 and AMD64): please run "sysctl vm.stats.pagequeue"
and report if the cache* values are zero (= bug in the cache detection code)
or not.

Based upon work by: Chad David <davidc@acns.ab.ca> [1]
Reviewed by: alc, arch (in 2004)
Discussed with: alc, Chad David, arch (in 2004)

Add an alternate ID for the arm920t (the real solution is to have
per-cpu class masks, but oh well).

Start all license statements with /*-

Be more verbose about cache capacities.

Add the hw.machine sysctl.

Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.