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267654 |
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19-Jun-2014 |
gjb |
Copy stable/9 to releng/9.3 as part of the 9.3-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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225736 |
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22-Sep-2011 |
kensmith |
Copy head to stable/9 as part of 9.0-RELEASE release cycle.
Approved by: re (implicit)
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205395 |
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20-Mar-2010 |
marius |
FPU_DEBUG requires <stdio.h>.
PR: 144900 Submitted by: Peter Jeremy MFC after: 3 days
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204974 |
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10-Mar-2010 |
marius |
- The OPSZ macro actually only does the right thing for int32 and int64 operands but not for double and extended double ones. Instead of trying to fix the macro just nuke it and unroll the loops in the correct way though as extended double operands turn out to be the only special case. - For FxTO{s,d,q} the source operand is int64 so rs2 has to be re-decoded after setting type accordingly as it's generally decoded using the low 2 bits as the type, which are 0 for these three instructions. - Similarly, in case of F{s,d,q}TOx the target is int64 so rd has to be re-decoded using not only the operand mask appropriate for int64 but also the correct register number encoding. - Use const where appropriate. - Wrap long lines.
Submitted by: Peter Jeremy (partly) MFC after: 3 days
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165903 |
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08-Jan-2007 |
imp |
Per Regents of the University of Calfornia letter, remove advertising clause.
# If I've done so improperly on a file, please let me know.
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124182 |
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06-Jan-2004 |
nectar |
Remove unused variables. Add required headers and function declarations.
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98373 |
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18-Jun-2002 |
jake |
Remove unneeded include of machine/emul.h.
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96422 |
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11-May-2002 |
jake |
Add a support macro to convert the 5-bit packed register field of a floating point instruction into a 6-bit register number for double and quad arguments. Make use of the new INSFPdq_RN macro where apporpriate; this is required for correctly handling the "high" fp registers (>= %f32). Fix a number of bugs related to the handling of the high registers which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64() should be used (the former can only access the low, single-precision, registers).
Submitted by: tmm
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95587 |
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27-Apr-2002 |
jake |
Emulate ldq and stq (load/store long double) instructions. GCC has started using these to load long doubles, but they aren't implemented in hardware on (at least) UltraSPARC I and II machines. Emulate popc in the user trap handler as well. Re-arrange slightly to make support functions more accessible.
Reviewed by: tmm
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94254 |
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08-Apr-2002 |
jake |
Rename some fields in struct frame to be compatible with NetBSD/OpenBSD, and add some compatibility defines. Add fields for ins and locals to struct reg also for the same reason; these aren't filled in yet because getting at those registers sucks and I'd rather not save them in the trapframe just for this. Reorder struct reg to be ABI compatible as well. Add needed include of machine/emul.h.
This gets pmdb (poor man's debugger) from OpenBSD mostly compiling but it doesn't work yet :(
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92986 |
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22-Mar-2002 |
obrien |
Fix the style of the SCM ID's. I believe have made all of libc .c's as consistent as possible.
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92055 |
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11-Mar-2002 |
tmm |
Fix some bugs that would prevent %fsr to be set correctly, and add support for fcmp and fcmpe instructions with a condition code specification other than %fcc0. This (primarily the first part) seems to fix a lot of problems that people were seeing, e.g. perl and gawk failures.
Reported and analyzed by: wollman
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91174 |
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23-Feb-2002 |
tmm |
Add userland floating point emulator code for sparc64. This is a port of the (never committed) in-kernel version (with some optimizations and cleanups), which in turn was ported from NetBSD.
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