Copy stable/11@r303970 to releng/11.0 as part of the 11.0-RELEASE
cycle.

Prune svn:mergeinfo from the new branch, and rename it to RC1.

Update __FreeBSD_version.

Use the quarterly branch for the default FreeBSD.conf pkg(8) repo and
the dvd1.iso packages population.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros.

The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with
a 5 port FE switch, gige WAN port, and all the same stuff you'd find on
its predecessor - the AR9331.

However, buried deep in here somewhere is also a PCIe EP/RC for various
applications and some other weird bits I don't yet know about.

This is enough to get the reference board up and booting. I haven't yet
had it pass lots of packets - I need to finalise the ethernet switch
bits and the GMAC configuration (ie, how the ethernet ports and switch
are wired up) and I'll bring that in when I commit the base configuration
files to use the thing.

The wifi stuff will come much later. I have to port that support from
Linux ath9k and extend our vendor HAL to support it.

The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order
to use it I need to get USB working fully so I can run root from there.

Thankyou to Qualcomm Atheros for access to the reference design board.

Details:

* Add register definitions from openwrt;
* It looks like a QCA955x but shrunk down to a QCA933x footprint, so
use the QCA955x bits and fix up the clock detection code to do the
QCA953x bits (they're very subtly different);
* Teach GPIO about it;
* Teach EHCI about it;
* Teach if_arge about it;
* Teach the CPU detection code about it.

Tested:

* AP143, QCA9533v2 SoC

Obtained from: Linux, Linux OpenWRT

Remove this; it's also in sys/conf/files.mips.

Add initial support for the QCA955x PCIe host controller.

The QCA955x looks a lot like the AR724x PCIe controller, except it
supports two root complexes. Unfortunately I only have one, so
although this code has started down the path of supporting more than
one, it's definitely not yet ready.

Tested:

* AP135 board (QCA9558 SoC), with the 11ac NIC swapped for an AR9380
PCIe NIC.

Notes:

* Yes, this driver isn't very pretty. I decided to commit what I have
versus holding onto something that isn't yet finished. It is enough
to bring up the above NIC and interrupt routing works, so it's a good
start.

* However, yes, the DDR flush routine hooks need to be fixed up.
I don't think I'm firing the right one at the moment.

Start fleshing out some MAC address helper functions.

A lot of these embedded boards don't have a unique MAC address per
device stored somewhere unique - sometimes they'll have one MAC
for both arge NICs; someties they'll have one MAC for both arge NICs
/and/ the ath NICs. In these instances, we need to derive device
specific MAC addresses from the base MAC address.

These functions will be used by some follow-up code that'll slot
into if_arge and if_ath.

Make the apb.c code optional behind ar71xx_apb rather than standard.

The QCA955x has more mux interrupts going on - and the AR934x actually does,
but I cheated and assigned wlan and pcie to the same interrupt line.
They are, there's just a status register mux that I should've been using.

Luckily this isn't too bad a change in itself - almost all of the
Atheros MIPS configurations use a _BASE file to inherit from.
Except PB92, which I should really fix up at some point.

The AR934x will use the legacy apb for now until I write its replacement.

The QCA955x SoC I'm doing bring-up on will have a separate qca955x_apb.c
implementation that includes hooking into IP2/IP3 and doing further
interrupt demuxing as appropriate.

Add initial Qualcomm Atheros QCA955x SoC support.

This adds the initial frequency poking and configures up enough
for it to boot and spit out data over the console.

There's still a whole bunch of work to do in the reset path
and devices to support this thing, but hey, it's alive!

ath> go 0x80050100
## Starting application at 0x80050100 ...
CPU platform: Atheros AR9558 rev 0
CPU Frequency=720 MHz
CPU DDR Frequency=600 MHz
CPU AHB Frequency=200 MHz
platform frequency: 720 MHz
CPU reference clock: 0 MHz
CPU MDIO clock: 40 MHz

Done at: hackathon
Obtained from: Linux OpenWRT, Qualcomm Atheros

Implement some initial AR934x support routines.

This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.

There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.

Tested:

* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)

Obtained from: Qualcomm Atheros; Linux/OpenWRT

Tie in the AR933x support into -HEAD.

Make MIPS24k PMC optional on "hwpmc_mips24k."

Requested by: juli

Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx.

The AR9330/AR9331 UART is a totally different thing, so having it included
with 'uart' is not going to work out.

Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.

* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
code does.

I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."

TODO:

* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
Linux OpenWRT. The current WAR has only been tested on the AR7240
and I'm not sure the way the BAR register is treated is "right".
The "fixup" method here is right when setting the BAR for local access -
ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
initial "fixup" BAR. It then restores the original BAR.
I'll have to read the ar724x PCI bus glue to see what other special cases
await.

Rework MIPS PMC code:

- Replace MIPS24K-specific code with more generic framework that will
make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
HWPMC_MIPS_BACKTRACE to override this limitation

Add some initial PCIe bridge support for the AR724x chipsets.

This is reported to work on the AR7240 based Ubiquiti Rocket M5
but I haven't tested it on that hardware. I also don't yet have
it fully working on the AR7242 based development board here;
probe/attach functions but the register space resource looks like
the endian-ness is wrong (0x10000000 instead of 0x00001000).o

Further digging will be required.

Submitted by: Luiz Otavio O Souza

In preparation for the AR724x PCIe bus code, make the AR71xx PCI bus
glue require 'device ar71xx_pci' .

Users of the AR71xx board configs will now require this for functioning
PCI:

device pci
device ar71xx_pci

Add AR71XX GPIO bus driver.

Add some initial AR724X chipset support.

This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.

Add initial Atheros AR91XX support.

This works well enough to bring a system up to single-user mode
using an MDROOT.

Known Issues:

* The EHCI USB doesn't currently work and will panic the kernel during
attach.
* The onboard ethernet won't work until the PLL routines have been
fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
hasn't yet been implemented.

Preparation work for supporting the AR91xx and AR724x.

* Implement a SoC probe function, from Linux, which determines the
SoC family, type and revision. This only probes the AR71xx series
SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
system frequencies) into using the cpuops introduced in an earlier commit.
Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
Ethernet PLL setup, other things I've likely missed) will be introduced in
subsequent commits.

Reviewed by: imp@
Obtained from: (partially) Linux

- Add driver for PCF2123, SPI real time clock/calendar

Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.

Submitted by: rpaulo@

Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.

Submitted by: rpaulo@

Merge from projects/mips to head by hand:

Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).

With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)

Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c
(which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.

- Add AR71XX watchdog timer driver

- Add SPI bus driver for ar71xx SoC

- Add pci bus space that translates byte order to little endian,
may be it will be merged with bus_space_reversed later
- Handle memory resources close to bus in order to control
bus_space_tag

- Add EHCI controller driver for AR71XX-based boards.

- Handle byte-order issue for non-word accesses to memory mapped
registers with ar71xx_bus_space_reversed. Note, that byte order
of values is handled by drivers. bus_spaces fixes only position
of register in word.
- Replace .hints hack for AR71XX UART with ar71xx_bus_space_reversed.

- Revert changes accidentally killed by merge operation

- Add integrated OHCI controller driver, just a
wrapper around generic ohci driver

- Add if_arge to build

- Add ar71xx PCI bridge implementation and link it to the build

- Add apb device. apb is bridge that connects UART, GPIO,
I2S and PCM to main bus
- Connect apb and uart_bus to build

- Use more generic name for atheros-based devices subdirectory. Keep old
naming scheme for files until we'll figure out common parts.

Suggested by: imp@

- First bits of Atheros' AR71XX port. Only UART supported ATM.