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303975 |
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11-Aug-2016 |
gjb |
Copy stable/11@r303970 to releng/11.0 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, and rename it to RC1.
Update __FreeBSD_version.
Use the quarterly branch for the default FreeBSD.conf pkg(8) repo and the dvd1.iso packages population.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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302408 |
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08-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle. Prune svn:mergeinfo from the new branch, as nothing has been merged here.
Additional commits post-branch will follow.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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300694 |
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25-May-2016 |
ian |
Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly.
Loves it: imp
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291426 |
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28-Nov-2015 |
mmel |
ARM: Implement atomic_swap_int(9). It's used in DRM2 code.
Approved by: kib (mentor)
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288491 |
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02-Oct-2015 |
kib |
FreeBSD does not support SMP on ARMv5. Since processor is always self-consistent, there is no need in anything but compiler barrier in the implementation of atomic_thread_fence_*() on ARMv5. Split implementation of fences for ARMv4/5 and ARMv6; the former use compiler barriers, the later also perform hardware barriers.
An issue which is fixed by the change is the faults from the CP15 coprocessor accesses in the user mode. This was uncovered by the pthread_once() changes in r287556.
Reported by: Mattia Rossi <mattia.rossi.mailinglists@gmail.com> Discussed with: alc, cognet, jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week
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285631 |
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16-Jul-2015 |
andrew |
Split out the arm and armv6 parts of atomic.h to new files. While here use __ARM_ARCH to determine which revision of the architecture is applicable.
Sponsored by: ABT Systems Ltd
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285283 |
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08-Jul-2015 |
kib |
Add the atomic_thread_fence() family of functions with intent to provide a semantic defined by the C11 fences with corresponding memory_order.
atomic_thread_fence_acq() gives r | r, w, where r and w are read and write accesses, and | denotes the fence itself.
atomic_thread_fence_rel() is r, w | w.
atomic_thread_fence_acq_rel() is the combination of the acquire and release in single operation. Note that reads after the acq+rel fence could be made visible before writes preceeding the fence.
atomic_thread_fence_seq_cst() orders all accesses before/after the fence, and the fence itself is globally ordered against other sequentially consistent atomic operations.
Reviewed by: alc Discussed with: bde Sponsored by: The FreeBSD Foundation MFC after: 3 weeks
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282776 |
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11-May-2015 |
andrew |
List both registers to use in the 64-bit atomic instructions. We will need these to build for Thumb-2.
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279543 |
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02-Mar-2015 |
ian |
Revert r279338. The casts are apparently bogus, despite the fact that they've been working in i386 (where this change came from).
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279338 |
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26-Feb-2015 |
ian |
Add casting to make atomic ops work for pointers. (Apparently nobody has ever done atomic ops on pointers before now on arm).
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
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279114 |
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21-Feb-2015 |
ian |
Correct a comment which was exactly backwards from reality.
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271398 |
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10-Sep-2014 |
andrew |
Unify interrupts bit definition and usage. While here remove PSR_C_bit.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>, Michal Meloun <meloun at miracle.cz> Differential Revision: https://reviews.freebsd.org/D754
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271310 |
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09-Sep-2014 |
ian |
Rename new to newval in inline asm code, to avoid clashes with C++ new. Also rename cmp to cmpval just to keep the asm variable names similar to the C variable names.
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269414 |
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02-Aug-2014 |
ian |
When arm 64-bit atomic ops are available, define ARM_HAVE_ATOMIC64. Use that symbol (which will be correct in both kernel and userland contexts) rather than just __arm__ to decide whether to use a local implementation.
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269405 |
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01-Aug-2014 |
ian |
Add 64-bit atomic ops for armv4, only for kernel code, mostly so that we don't need any #ifdef stuff to use atomic_load/store_64() elsewhere in the kernel. For armv4 the atomics are trivial to implement for kernel code (just disable interrupts), less so for user mode, so this only has the kernel mode implementations for now.
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269403 |
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01-Aug-2014 |
ian |
Add 64-bit atomic ops for armv6. The only safe way to access a 64-bit value shared across multiple cores is with atomic_load_64() and atomic_store_64(), because the normal 64-bit load/store instructions are not atomic on 32-bit arm. Luckily the ldrexd/strexd instructions that are atomic are fairly cheap on armv6. Because it's fairly simple to do, this implements all the ops for 64-bit, not just load/store.
Reviewed by: andrew, cognet
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265861 |
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11-May-2014 |
ian |
Make the hardware memory and instruction barrier functions work on armv4 and armv5 as well.
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261393 |
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02-Feb-2014 |
ian |
Update all arm code that manipulates the PSR registers to use modern syntax.
It turns out the version of gas we're using interprets the old '_all' mask as 'fc' instead of 'fsxc'. That is, "all" doesn't really mean "all".
This was the cause of the "wrong-endian register restore" bug that's been causing problems with some cortex-a9 chips. The 'endian' bit in the spsr register would never get changed (it falls into the 'x' mask group) and the first return-from-exception would fail if the chip had powered on with garbage in the spsr register that included the big-endian bit. It's unknown why this affected only certain cortex-a9 chips.
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257189 |
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26-Oct-2013 |
andrew |
Fix an itt instruction. We need to execute both the mov and b instructions when building for Thumb.
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253489 |
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20-Jul-2013 |
andrew |
Start adding support to build bits of our code using the Thumb-2 instruction set. Thumb-2 requires an if-then instruction to implement conditional codes.
When building for ARM mode the it-then instructions do not generate any assembled instruction as per the ARMv7-A Architecture Reference Manual, and are safe to use.
While this allows the atomic instructions to be built, it doesn't mean we fully support Thumb code. It works in small tests, but is still known to fail in a large number of places.
While here add a check for the armv6t2 architecture.
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245475 |
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15-Jan-2013 |
cognet |
Don't define rel/acq variants of some atomic operations as the regular version for armv6.
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245135 |
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07-Jan-2013 |
gonzo |
Implement barriers for AMRv6 and ARMv7
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Reviewed by: ian, cognet
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241080 |
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01-Oct-2012 |
andrew |
Fix the clobber list on the atomic operators that do comparisons. Without this some compilers will place a cmp instruction before the atomic operation and expect to be able to use the result afterwards. By adding "cc" to the list of used registers we tell the compiler to not do this.
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239268 |
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15-Aug-2012 |
gonzo |
Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
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238347 |
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10-Jul-2012 |
imp |
Revert committal of local change accidentally swept up in r238329.
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238329 |
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10-Jul-2012 |
imp |
Remove some unused variables/externs that have been copied too many times...
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236992 |
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13-Jun-2012 |
imp |
trim trailing whitespace
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190603 |
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31-Mar-2009 |
cognet |
Fix the userland, RAS, version of atomic_fetchadd_32 : return the correct value, and do not store the wrong one in the supplied pointer.
Submitted by: Mark Tinguely <tinguely casselton net>
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188085 |
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03-Feb-2009 |
sam |
force atomic_cmpset_ptr types to match atomic_cmpset_32; this matches what powerpc does
Submitted by: stass MFC after: 2 weeks
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185162 |
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22-Nov-2008 |
kmacy |
- bump __FreeBSD version to reflect added buf_ring, memory barriers, and ifnet functions
- add memory barriers to <machine/atomic.h> - update drivers to only conditionally define their own
- add lockless producer / consumer ring buffer - remove ring buffer implementation from cxgb and update its callers
- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to allow drivers to efficiently manage multiple hardware queues (i.e. not serialize all packets through one ifq) - expose if_qflush to allow drivers to flush any driver managed queues
This work was supported by Bitgravity Inc. and Chelsio Inc.
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175982 |
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05-Feb-2008 |
raj |
Improve ARM_TP_ADDRESS and RAS area.
De-hardcode usage of ARM_TP_ADDRESS and RAS local storage, and move this special purpose page to a more convenient place i.e. after the vectors high page, more towards the end of address space. Previous location (0xe000_0000) caused grief if KVA was to go beyond the default limit.
Note that ARM world rebuilding is required after this change since the location of ARM_TP_ADDRESS is shared between kernel and userland.
Submitted by: Grzegorz Bernacki (gjb AT semihalf dot com) Reviewed by: imp Approved by: cognet (mentor)
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174170 |
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02-Dec-2007 |
cognet |
Close a race.
The RAS implementation would set the end address, then the start address. These were used by the kernel to restart a RAS sequence if it was interrupted. When the thread switching code ran, it would check these values and adjust the PC and clear them if it did.
However, there's a small flaw in this scheme. Thread T1, sets the end address and gets preempted. Thread T2 runs and also does a RAS operation. This resets end to zero. Thread T1 now runs again and sets start and then begins the RAS sequence, but is preempted before the RAS sequence executes its last instruction. The kernel code that would ordinarily restart the RAS sequence doesn't because the PC isn't between start and 0, so the PC isn't set to the start of the sequence. So when T1 is resumed again, it is at the wrong location for RAS to produce the correct results. This causes the wrong results for the atomic sequence.
The window for the first race is 3 instructions. The window for the second race is 5-10 instructions depending on the atomic operation. This makes this failure fairly rare and hard to reproduce.
Mutexs are implemented in libthr using atomic operations. When the above race would occur, a lock could get stuck locked, causing many downstream problems, as you might expect.
Also, make sure to reset the start and end address when doing a syscall, or a malicious process could set them before doing a syscall.
Reviewed by: imp, ups (thanks guys) Pointy hat to: cognet MFC After: 3 days
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173999 |
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27-Nov-2007 |
cognet |
In atomic_fetchadd_32(), do not blindly increase the value of %3. It should just contain the value we want to add, as if we're interrupted between the add and the str, we will restart from the beginning. Just use a register we can scratch instead.
MFC After: 1 week
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165786 |
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05-Jan-2007 |
ticso |
MFp4: Add missing atomic functions Based on a patch by: des
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164059 |
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07-Nov-2006 |
cognet |
Add atomic_cmpset_acq_32.
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158593 |
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15-May-2006 |
cognet |
Add definitions for atomic_subtract_rel_32, atomic_add_rel_32 and atomic_load_acq_32, needed for hwpmc.
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157725 |
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13-Apr-2006 |
cognet |
Disable/enable fiqs as well as irqs.
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155391 |
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06-Feb-2006 |
cognet |
Use memory clobbers, to be on the safe side. Suggested by: jhb
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155355 |
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05-Feb-2006 |
cognet |
Backout rev 1.12. It would have been a good thing, if gcc was smart enough not to generate bad code.
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153276 |
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09-Dec-2005 |
cognet |
A #define is not enough, we need to cast from u_long * to uint32_t *.
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153275 |
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09-Dec-2005 |
cognet |
Define atomic_whatever_long
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151340 |
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14-Oct-2005 |
jhb |
Whitespace.
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151334 |
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14-Oct-2005 |
jhb |
Change the userland atomic operations on arm to use memory operands for the modified memory rather than using register operands that held a pointer to the memory. The biggest effect is that we now correctly tell the compiler that these functions change the memory that these functions modify.
Reviewed by: cognet
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150627 |
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27-Sep-2005 |
jhb |
Add a new atomic_fetchadd() primitive that atomically adds a value to a variable and returns the previous value of the variable.
Tested on: i386, alpha, sparc64, arm (cognet) Reviewed by: arch@ Submitted by: cognet (arm) MFC after: 1 week
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148453 |
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27-Jul-2005 |
jhb |
Add extra constraints to tell the compiler that the memory be modified in the arm __swp() and sparc64 casa() and casax() functions is actually being used as an input and output and not just the value of the register that points to the memory location. This was the underlying source of the mbuf refcount problems on sparc64 a while back. For arm this should be a nop because __swp() has a constraint to clobber all memory which can probably be removed now.
Reviewed by: alc, cognet MFC after: 1 week
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148067 |
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15-Jul-2005 |
jhb |
Convert the atomic_ptr() operations over to operating on uintptr_t variables rather than void * variables. This makes it easier and simpler to get asm constraints and volatile keywords correct.
MFC after: 3 days Tested on: i386, alpha, sparc64 Compiled on: ia64, powerpc, amd64 Kernel toolchain busted on: arm
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147555 |
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23-Jun-2005 |
jhb |
Fix a typo.
Approved by: re (scottl)
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146591 |
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24-May-2005 |
cognet |
Make sure we clean the RAS start address once we're done. This fixes the random segfaults which occurs at high interrupts rate.
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144761 |
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07-Apr-2005 |
cognet |
Import a basic implementation of the restartable atomic sequences to provide atomic operations to userland (this is OK for UP only, but SMP is still so far away).
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139735 |
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05-Jan-2005 |
imp |
Start all license statements with /*-
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139021 |
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18-Dec-2004 |
cognet |
Make sure gcc doesn't generate something such as swp r3, r4, [r3] for __swp, as it has unpredictable results.
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137282 |
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05-Nov-2004 |
cognet |
Disable interrupts for atomic_cmpset_32, this one is just not atomic. Don't export it to userland.
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137222 |
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04-Nov-2004 |
cognet |
Try to implement atomic operations using swp, instead of disabling interrupts.
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129198 |
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14-May-2004 |
cognet |
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
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