MFC 340164,340168,340170: Add custom cpu_lock_delay() for x86.

340164:
Add a KPI for the delay while spinning on a spin lock.

Replace a call to DELAY(1) with a new cpu_lock_delay() KPI. Currently
cpu_lock_delay() is defined to DELAY(1) on all platforms. However,
platforms with a DELAY() implementation that uses spin locks should
implement a custom cpu_lock_delay() doesn't use locks.

340168:
Add a delay_tsc() static function for when DELAY() uses the TSC.

This uses slightly simpler logic than the existing code by using the
full 64-bit counter and thus not having to worry about counter
overflow.

340170:
Add a custom implementation of cpu_lock_delay() for x86.

Avoid using DELAY() since it can try to use spin locks on CPUs without
a P-state invariant TSC. For cpu_lock_delay(), always use the TSC if
it exists (even if it is not P-state invariant) to delay for a
microsecond. If the TSC does not exist, read from I/O port 0x84 to
delay instead.

PR: 228768

MFC 332906,332907,332976,333679,336053: Expand testing of breakpoints.

332906:
Extend support for ptrace() tests using breakpoints.

- Use a single list of platforms to define HAVE_BREAKPOINT for platforms
that expose a functional breakpoint() inline to userland. Replace
existing lists of platform tests with HAVE_BREAKPOINT instead.
- Add support for advancing PC past a breakpoint inserted via breakpoint()
to support the existing ptrace__PT_CONTINUE_different_thread test on
non-x86 platforms (x86 advances the PC past the breakpoint instruction,
but other platforms do not). This is implemented by defining a new
SKIP_BREAK macro which accepts a pointer to a 'struct reg' as its sole
argument and modifies the contents to advance the PC. The intention is
to use it in between PT_GETREGS and PT_SETREGS.

332907:
Expose breakpoint() to userland from <machine/cpufunc.h> on MIPS.

Enable ptrace() tests using breakpoint on MIPS as well.

332976:
Shorten some recently-added lines that are an extra indent over 80 columns.

333679:
Export a breakpoint() function to userland for riscv.

As a result, enable tests using breakpoint() on riscv.

336053:
Export a breakpoint() function to userland for arm and arm64.

Enable ptrace() tests using breakpoint() on these architectures.

MFC r329859,r329860: Float protection in stand

r329859: Do not include float interfaces when using libsa.

We don't support float in the boot loaders, so don't include
interfaces for float or double in systems headers. In addition, take
the unusual step of spiking double and float to prevent any more
accidental seepage.

r329860: Floaty McFloatface is funnier...

MFC r316648:

Corrected misspelled versions of rendezvous.

The MFC maintains smp_no_rendevous_barrier() as a symbol alias of
smp_no_rendezvous_barrier().

__FreeBSD_version bumped to indicate presence of the new name
smp_no_rendezvous_barrier().

Reviewed by: gnn, jhb (email), kib
Differential Revision: https://reviews.freebsd.org/D10313

MFC r326971, r327047 (by ian), r327053 (by marius), r327074, r327097:
Add atomic_load(9) and atomic_store(9) operations.

MFC 323580,323933,323934,324814,324817: Enable AT_HWCAP on arm.

I reused the SV_HWCAP stub to cover the sv_hwcap2 field as well.

323580:
Add AT_HWCAP flags for VFP settings for FreeBSD/arm.

These flags match the meaning and value of flags in Linux, though
Linux has many more flags.

323933:
Correct HWCAP_VFP3* values to match Linux.

323934:
Detect NEON and set HWCAP_NEON if present.

324814:
Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.

324817:
Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports.

Tested by: mmel

MFC 323579,323585: Add AT_HWCAP and AT_EHDRFLAGS on all platforms.

To preserve KBI on stable/11, a new SV_HWCAP flag is added which
indicates if the sv_hwcap field is present and valid to avoid examining
the field in old modules. Only sysentvec's which wish to use sv_hwcap
need to set the flag in stable/11.

323579:
Add AT_HWCAP and AT_EHDRFLAGS on all platforms.

A new 'u_long *sv_hwcap' field is added to 'struct sysentvec'. A
process ABI can set this field to point to a value holding a mask of
architecture-specific CPU feature flags. If an ABI does not wish to
supply AT_HWCAP to processes the field can be left as NULL.

The support code for AT_EHDRFLAGS was already present on all systems,
just the #define was not present. This is a step towards unifying the
AT_* constants across platforms.

323585:
Add AT_EHDRFLAGS and AT_HWCAP on amd64.

x86 has two separate (but identical) list of AT_* constants and the
earlier commit to add AT_HWCAP only updated the i386 list.

MFC r319871:
Make struct syscall_args visible to userspace compilation environment
from machine/proc.h, consistently on all architectures.

MFC efivar(8) (by imp):

List of revisions merged:
r307070
r307071
r307072
r307074
r307189
r307224
r307339
r307390
r307391
r309776
r314231
r314232
r314615
r314616
r314617
r314618
r314619
r314620
r314621
r314623
r314890
r314925
r314926
r314927
r314928
r315770
r315771

Discussed with: gjb (re), imp
Sponsored by: The FreeBSD Foundation

MFC r311169,r311898,r312925,r312973,r312975,r313007,r313040,r313080,
r313254,r313341

amd64: add atomic_fcmpset

==

sparc64: add atomic_fcmpset

==

Implement atomic_fcmpset_* for arm and arm64.

==

Add atomic_fcmpset_*() inlines for powerpc

Summary:
atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the read value
from the target memory location into the 'old' pointer in the case of failure.

==

i386: add atomic_fcmpset

==

Don't retry a lost reservation in atomic_fcmpset()

The desired behavior of atomic_fcmpset_() is to always exit on error. Instead
of retrying on lost reservation, leave the retry to the caller, and return

==

Add atomic_fcmpset_*() inlines for MIPS

atomic_fcmpset_*() is analogous to atomic_cmpset(), but saves off the
read value from the target memory location into the 'old' pointer.

==

i386: fixup fcmpset

An incorrect output specifier was used which worked with clang by accident,
but breaks with the in-tree gcc version.

While here plug a whitespace nit.

==

Implement atomic_fcmpset_*() for RISC-V.

==

Use 64bit store instruction in atomic_fcmpset_64.

MFC r313194:
Define the vm_ooffset_t and vm_pindex_t types as machine-independend.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Remove duplicate define.

Increase the size and alignment of the setjmp buffer.
This is required for future CPU extentions.

Reviewed by: brooks
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Add initial DTrace support for RISC-V.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Rework the list of all pmaps: embed the list link into pmap.

Add the non-standard "IO interrupt" vector used by lowRISC.
For now they provide UART irq only.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Move arm's devmap to some generic place, so it can be used
by other architectures.

Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D6091
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

o Implement shared pagetables and switch from 4 to 3 levels page
memory system.

RISC-V ISA has only single page table base register for both kernel
and user addresses translation. Before this commit we were using an
extra (4th) level of pagetables for switching between kernel and user
pagetables, but then realized FPGA hardware has 3-level page system
hardcoded. It is also become clear that the bitfile synthesized for
4-level system is untested/broken, so we can't use extra level for
switching.

We are now share level 1 of pagetables between kernel and user VA.
This requires to keep track of all the user pmaps created and once we
adding L1 page to kernel pmap we have to add it to all the user pmaps.

o Change the VM layout as we must have topmost bit to be 1 in the
selected page system for kernel addresses and 0 for user addresses.
o Implement pmap_kenter_device().
o Create the l3 tables for the early devmap.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Add support for ddb(4).

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

o Use uint64_t for page number as it doesn't fit uint32_t.
o Implement growkernel bits for L1 level of pagetables.

This allows us to boot with 128GB of physical memory.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Add support for symmetric multiprocessing (SMP).

Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.

This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).

Invalidate entire TLB cache as it is the only way yet.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Remove duplicates.

Increase kernel and user VA space.
This allows us to boot with more than 128MB of physical memory.

Sponsored by: DARPA, AFRL
Sponsored by: HEIF5

Add the implementation of atomic_swap_32().

Use better form representing 32 x 128-bit floating-point registers.

Suggested by: kib

Use __uint64_t type for floating point registers
as compiler don't know about __uint128_t yet.

Discussed with: theraven, kib

Access pcpup using gp register.

Reuse gp register for pcpu pointer.

gp (global pointer) is used by compiler in userland only,
so re-use it for pcpup in kernel, save it on stack on switching
out to userland and load back on return to kernel.

Discussed with: jhb, andrew, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D5178

Correct RISC-V exception types.

Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by: andrew, imp, kib
Sponsored by: DARPA, AFRL
Sponsored by: HEIF5
Differential Revision: https://reviews.freebsd.org/D4554