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295972 |
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24-Feb-2016 |
br |
Add support for symmetric multiprocessing (SMP).
Tested on Spike simulator with 2 and 16 cores (tlb enabled), so set MAXCPU to 16 at this time.
This uses FDT data to get information about CPUs (code based on arm64 mp_machdep).
Invalidate entire TLB cache as it is the only way yet.
Sponsored by: DARPA, AFRL Sponsored by: HEIF5
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295041 |
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29-Jan-2016 |
br |
Welcome the RISC-V 64-bit kernel.
This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD.
RISC-V is a completely open ISA that is freely available to academia and industry.
Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project.
This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory.
FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv
Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
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