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295138 |
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02-Feb-2016 |
adrian |
Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options
This revision does the following renames: CPU_MIPS24KC -> CPU_MIPS24K CPU_MIPS74KC -> CPU_MIPS74K CPU_MIPS1004KC -> CPU_MIPS1004K
It also adds the following new CPU_MIPSxxx options: CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV
CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the MIPSxxxxK CPU has no FPU. It would be better if the CPUs are named after their standard functionalities only and the presence or absence of FPU can then be controlled via the CPU_HAVEFPU option.
I will send out another dependent revision that moves MIPS 32 r2 and r3 CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.
Submitted by: Stanislav Galabov <sgalabov@gmail.com> Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D5077
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284959 |
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30-Jun-2015 |
markm |
Huge cleanup of random(4) code.
* GENERAL - Update copyright. - Make kernel options for RANDOM_YARROW and RANDOM_DUMMY. Set neither to ON, which means we want Fortuna - If there is no 'device random' in the kernel, there will be NO random(4) device in the kernel, and the KERN_ARND sysctl will return nothing. With RANDOM_DUMMY there will be a random(4) that always blocks. - Repair kern.arandom (KERN_ARND sysctl). The old version went through arc4random(9) and was a bit weird. - Adjust arc4random stirring a bit - the existing code looks a little suspect. - Fix the nasty pre- and post-read overloading by providing explictit functions to do these tasks. - Redo read_random(9) so as to duplicate random(4)'s read internals. This makes it a first-class citizen rather than a hack. - Move stuff out of locked regions when it does not need to be there. - Trim RANDOM_DEBUG printfs. Some are excess to requirement, some behind boot verbose. - Use SYSINIT to sequence the startup. - Fix init/deinit sysctl stuff. - Make relevant sysctls also tunables. - Add different harvesting "styles" to allow for different requirements (direct, queue, fast). - Add harvesting of FFS atime events. This needs to be checked for weighing down the FS code. - Add harvesting of slab allocator events. This needs to be checked for weighing down the allocator code. - Fix the random(9) manpage. - Loadable modules are not present for now. These will be re-engineered when the dust settles. - Use macros for locks. - Fix comments.
* src/share/man/... - Update the man pages.
* src/etc/... - The startup/shutdown work is done in D2924.
* src/UPDATING - Add UPDATING announcement.
* src/sys/dev/random/build.sh - Add copyright. - Add libz for unit tests.
* src/sys/dev/random/dummy.c - Remove; no longer needed. Functionality incorporated into randomdev.*.
* live_entropy_sources.c live_entropy_sources.h - Remove; content moved. - move content to randomdev.[ch] and optimise.
* src/sys/dev/random/random_adaptors.c src/sys/dev/random/random_adaptors.h - Remove; plugability is no longer used. Compile-time algorithm selection is the way to go.
* src/sys/dev/random/random_harvestq.c src/sys/dev/random/random_harvestq.h - Add early (re)boot-time randomness caching.
* src/sys/dev/random/randomdev_soft.c src/sys/dev/random/randomdev_soft.h - Remove; no longer needed.
* src/sys/dev/random/uint128.h - Provide a fake uint128_t; if a real one ever arrived, we can use that instead. All that is needed here is N=0, N++, N==0, and some localised trickery is used to manufacture a 128-bit 0ULLL.
* src/sys/dev/random/unit_test.c src/sys/dev/random/unit_test.h - Improve unit tests; previously the testing human needed clairvoyance; now the test will do a basic check of compressibility. Clairvoyant talent is still a good idea. - This is still a long way off a proper unit test.
* src/sys/dev/random/fortuna.c src/sys/dev/random/fortuna.h - Improve messy union to just uint128_t. - Remove unneeded 'static struct fortuna_start_cache'. - Tighten up up arithmetic. - Provide a method to allow eternal junk to be introduced; harden it against blatant by compress/hashing. - Assert that locks are held correctly. - Fix the nasty pre- and post-read overloading by providing explictit functions to do these tasks. - Turn into self-sufficient module (no longer requires randomdev_soft.[ch])
* src/sys/dev/random/yarrow.c src/sys/dev/random/yarrow.h - Improve messy union to just uint128_t. - Remove unneeded 'staic struct start_cache'. - Tighten up up arithmetic. - Provide a method to allow eternal junk to be introduced; harden it against blatant by compress/hashing. - Assert that locks are held correctly. - Fix the nasty pre- and post-read overloading by providing explictit functions to do these tasks. - Turn into self-sufficient module (no longer requires randomdev_soft.[ch]) - Fix some magic numbers elsewhere used as FAST and SLOW.
Differential Revision: https://reviews.freebsd.org/D2025 Reviewed by: vsevolod,delphij,rwatson,trasz,jmg Approved by: so (delphij)
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283097 |
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19-May-2015 |
adrian |
QCA955x / AP135 platform tidyups.
* Change mips24k -> mips74k for hwpmc, but leave it disabled for now. * don't build pci by default. * build pci and qca955x_pci for AP135, as theres a PCIe NIC. * don't build a hwpmc module, it doesn't really work out well for the mips boards at the moment. * add ipfw and DEFAULT_TO_ACCEPT.
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279513 |
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02-Mar-2015 |
adrian |
Bring over the initial QCA955x SoC support framework.
This is enough to bring up the basic SoC support.
What works thus far:
* The mips74k core, pll setup, and UART (or else well, stuff would be really difficult..) * both USB 2.0 EHCI controllers * on-board 2GHz 3x3 wifi (the other variant has 2GHz/5GHz wifi on-chip); * arge0 - not yet sure why arge1 isn't firing off interrupts and thus handling traffic, but I will soon figure it out and fix it here.
Tested:
* AP135 reference design, QCA9558 SoC, pretending to be an 11n 2GHz AP.
TODO:
* There's an interrupt mux hooking up devices to IP2 and IP3 - but it's not a read-and-clear or write-to-clear register. So, trying to use it naively like I have been ends up with massive interrupt storms. For now the things that share those interrupts can just take them as shared interrupts and try to play nice.
* There's two PCIe root complexes /and/ one of them can actually be a PCIe device endpoint. Yes, you heard right. I have to teach the AR724x PCIe bridge code to handle multiple instances with multiple memory/irq regions, and then there'll be RC support, but EP support isn't on my TODO list.
* I'm not sure why arge1 isn't up and running. I'll go figure that out soon and fix it here.
Thankyou to Qualcomm Atheros for providing me with hardware and an abundance of documentation about these things.
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