Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

* Add ethernet MAC configuration from the EEPROM for arge0/arge1
* The AR9344 switch has 5 ports in use, not four.

Tested:

* DB120 reference board

Add the DB120 specific hints for the AR8327.

Tested:

* DB120

Add the AR8327 bits to the DB120 config file.

There's plenty of hints that I haven't yet fleshed out and are hardcoded
in arswitch_8327.c. They're listed here (from OpenWRT) for completeness.

This is enough to get the thing up, running and pinging.

Note that the mdiobus for the on-switch switch changes - the AR8327
probes first, which exposes mdio1, and thus the arge1 mdiobus will probe
and attach as mdio2. That is what the AR9344 on-chip switch has to
attach to.

Tested:

* Qualcomm Atheros DB120

Enable use of the PCIe connected wifi on the DB120 (AR9344) board.

The on-board NIC is an 3x3 AR9380 with 5GHz only.

* enable pci code in AR9344_BASE
* enable ath_pci and the firmware loading bits in DB120
* add in the relevant hints in DB120.hints to inform the probe/attach
code where the PCIe fixup data is for the onboard chip.

This is only relevant for a default development board. I also have a
DB120 with the on-board PCIe wifi NIC disabled and it's exposed as
a real PCIe slot (to put normal PCIe NICs in); the fixup code will need
to be disabled to make this work correctly.

Tested:

* DB120

Add the ath0 EEPROM hints required to detect the on-chip wifi.

This allows the on-chip wifi to work; however it's not yet fully
tested.

ath0: Vendor=0x168c, Device=0x0031
ath0: Vendor=0x168c, Device=0x0031
ath0: <Atheros AR934x> at mem 0x18100000-0x1811ffff irq 0 on nexus0
...
ath0: [HT] enabling HT modes
ath0: [HT] enabling short-GI in 20MHz mode
ath0: [HT] 1 stream STBC receive enabled
ath0: [HT] 1 stream STBC transmit enabled
ath0: [HT] 2 RX streams; 2 TX streams

Tested:

* DB120 development board

Now that all of the on-chip switch and basic platform support is updated,
we can now add all the hardware bits for the DB120.

* arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently
no support for. However, the bootloader on this board does set it up as
a basic switch so we can at least _use_ it ourselves.

So we should at least configure the arge0 side of things, including the GMAC
register.

* .. the GMAC config peels off arge0 from the internal switch and exposes it
as an RGMII to said AR8327.

* arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also
needs configuring.

* Add support for the NOR flash layout.

* Add support for the wifi (which works, with bugs, but it works.)

What's missing!

* No GPIO stuff yet!
* No sound (I2S) and no NAND flash support yet, sorry!
* The normal DB120 has an external AR95xx wifi chip on PCIe but with the
actual calibration data in the NOR flash. My DB120 has been modified
to let me use the PCIe slot as a normal PCIe slot. I'll add the "default"
settings later when I have access to a non-modified one.
* Other stuff, like why the wifi unit gets upset and spits out stuck beacons
and interrupt storms everywhere. Sigh.

Tested:

* DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user
mode.

Add some initial board support for the AR934x and the Qualcomm Atheros
DB120 development board.

The AR934x SoCs are a MIPS74k based system with increased RAM addressing
space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3
on-board dual-band wifi.

This support isn't complete by any stretch; it's just enough to bring
the board up for others to tinker with. Notably, the MIPS74k support
is broken. However it boots enough to echo some basic probe/attach
messages, before dying somewhere in the TLB code.

Thankyou to Qualcomm Atheros for their continued support of me doing
open source work with their hardware.

Tested:

* AR9344, mips74k