Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Make pl310_print_config static, it's not called out of pl310.c

Sponsored by: ABT Systems Ltd

Remove trailing whitespace from sys/arm/arm

- Make interrupt resource optional: some upstream FDT blobs (e.g. TI's) do
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled, it's not vital for
normal operations.
- Fix intrhook allocation/initialization

Accept the documented FDT compatible string for the PL310 cache controller
as well as the non-standard string we've been using for a couple years.

Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Because that's earlier than interrupts are available, set up deferred
configuration of interrupts (which are used only for debugging).

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.

Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.

Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.

Some of the pl310 configuration registers cannot be changed while the
controller is active, so if there is any platform-specific init to be done
it must happen before enabling the controller.

The controller should not be enabled upon entry to the kernel, but u-boot
has recently developed the bad habit of leaving caches enabled when
launching the kernel, and since we have no control over that source code
we have to do our best to cope with it. The PL310 manual doesn't document
a safe sequence for disabling the controller, but the sequence used here
(force write-through mode and disable linefill allocations, then clean and
invalidate the current contents before disabling the hardware) appears to
be sound both by analysis and empirical testing.

These changes were developed and tested in collaboration with
Svatopluk Kraus <onwahe@gmail.com>.

Reviewed by: cognet@

Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.

Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.

Move duplicated code to print l2 cache config into the common code.

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.

Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.

Invalidate the entire L2 cache before enabling it. Say whether it
has been enabled or disabled.

The errata 727915 requires a different workaround for r2p0, we have to
explicitely clean/invalidate every cache line using way/set operations.

Remove old declarations.

Release version check for erratum 727915 workaround in
l2_wbinv_range function implementation causes function
fail to flush caches for chip with RTL number 0x7. I failed
to find official PL310 revision with this RTL number
so further research on this matter required.

Fix the build:

* Use pl310_softc when the softc is otherwise unavailable.
* Use the correct spelling of sc_rtl_revision.

Only work around errata when we are on a part where the erratum applies.

Reviewed by: gonzo

PL310 driver update:

- Add pl310.disable tunable to disable L2 cache altogether. In
order to make sure that it's 100% disabled we use cache event
counters for cache line eviction and read allocate events
and panic if any of these counters increased. This is purely
for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
unsecure mode, so use platform-specific functions for
these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
prefetch is enabled in OMAP4-specific intialization

Make sure the address starts on a cache line boundary.

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms