MFC r310791:

[qemu] Fix VERSATILEPB kernel boot in QEMU broken by r300968

QEMU does not implement hardware debug registers so when
dbg_monitor_is_enabled is called kernel receives "invalid instruction"
exception. QEMU implements only DIDR register and on read returns all
zeroes to indicate that it doesn't support other registers. Real
hardware has Version bits set.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Improve ARM debug_monitor for SMP machines

- Reset debug architecture and enable monitor for secondary
CPUs in init_secondary() rather than when configuring watchpoint, etc.
- Disable HW debugging capabilities when one of the CPU cores fails
to set up.
- Use dbg_capable() in a more atomic manner to avoid any mismatch
between CPUs.

Differential Revision: https://reviews.freebsd.org/D6009

Fix debug_monitor code for older ARMs (ARM11)

- Enable monitor mode prior to accessing watchpoint
registers for v6, v6.1 architectures.
- Fix configuration scheme for v6, v6.1 and v7 Debug Archs
- Enable monitor unconditionally and for good instead
of enabling and disabling it (needed for single stepping
on on v6/v6.1)

Tested on RPI-B and Arndale

Differential Revision: https://reviews.freebsd.org/D6008

As <machine/param.h> is included from <sys/param.h>, there is no need
to include it explicitly when <sys/param.h> is already included.

Reviewed by: alc, kib
Differential Revision: https://reviews.freebsd.org/D5378

ARM: RPI-B kernel was broken by r294740. Make it functional again.

SMP support for ARMv6/v7 HW watchpoints

Use per-CPU structure to store HW watchpoints registers state
for each CPU present in the system. Those registers will be restored
upon wake up from the STOP state if requested by the debug_monitor
code. The method is similar to the one introduced to AMD64.

We store all possible 16 registers for HW watchpoints
(maximum allowed by the architecture).
HW breakpoints are not maintained since they are used for single
stepping only.

Pointed out by: kib
Reviewed by: wma
No strong objections from: kib
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4338

Introduce support for HW watchpoints and single stepping for ARMv6/v7

Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.

HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.

Reviewed by: imp
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037