MFC r328467:

Implement mitigation for Spectre version 2 attacks on ARMv7.

MFC r319896,r320054:

r319896:
Implement tunable CPU quirks. These quirks are intended for optimizing CPU
performance, not for applying errata workarounds. Nobody can expect that
CPU with unfixed errata is stable enough to execute the kernel until quirks
are applied.
r320054:
Manually load tunable CPU quirks. These are needed too early, far before
SYSINIT is processed.

MFC r324821:

Fix spelling.

MFC 323580,323933,323934,324814,324817: Enable AT_HWCAP on arm.

I reused the SV_HWCAP stub to cover the sv_hwcap2 field as well.

323580:
Add AT_HWCAP flags for VFP settings for FreeBSD/arm.

These flags match the meaning and value of flags in Linux, though
Linux has many more flags.

323933:
Correct HWCAP_VFP3* values to match Linux.

323934:
Detect NEON and set HWCAP_NEON if present.

324814:
Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
- expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
same way as for AT_HWCAP.

324817:
Fullify implementation of AT_HWCAP and AT_HWCAP2 for ARMv6,7.
This makes elf_aux_info(3) useable for ARM ports.

Tested by: mmel

MFC r306901:

ARM: Split identify_arm_cpu() into ARMv4 and ARMv6 variant.
On ARMv6, be more verbose about supported CPU features and/or
optional instructions.

MFC r306755:

ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a
functional change.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

ARM: Introduce new cpu-v4.h header and move all ARMv4 specific code
from cpu-v6.h to it.
Remove unneeded cpu-v6.h includes.

Set the correct values in the arm aux control register, based on chip type.

The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>

Remove trailing whitespace from sys/arm/arm

Retrieve the cache parms in the proper arch-specific way.

Submitted by: Michal Meloun <meloun@miracle.cz>

Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.

Submitted by: Michal Meloun

Add logic for handling new-style ARM cpu ID info.

Submitted by: Michal Meloun <meloun@miracle.cz>

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz