Revert r330897:

This was intended to be a non-functional change. It wasn't. The commit
message was thus wrong. In addition it broke arm, and merged crypto
related code.

Revert with prejudice.

This revert skips files touched in r316370 since that commit was since
MFCed. This revert also skips files that require $FreeBSD$ property
changes.

Thank you to those who helped me get out of this mess including but not
limited to gonzo, kevans, rgrimes.

Requested by: gjb (re)

Partial merge of the SPDX changes

These changes are incomplete but are making it difficult
to determine what other changes can/should be merged.

No objections from: pfg

MFC r306704,r308406:

r306704:
ARM: Remove next bunch of unused cpu_functions from ARMv6.
r308406:
Only include sys/boot.h if LINUX_BOOT_ABI is defined

MFC r306631,r306640,r306641,r306650,r306656:

r306631:
Use C99 designated initializers to create the armv6 cpu_functions structs.
This will help with a later cleanup of what functions we implement.
r306640:
Only define the CF_* macros on ARMv4/v5. They are unused on armv6.
r306641:
Remove the parts of cpu_functions from armv6 that are unused on that
architecture.
r306650:
Add the Cortex-A{53,57,72} ID register values. These can all run 32-bit
code so could run a 32-bit kernel.
r306656:
Use the cortex functions when booting on one of the Cortex-A ARMv8 CPUs.
This list is incomplete, however we don't have the ID values for the
missing Cortex-A32 or A35.

MFC r312292, r313573:

Stop including sys/types.h from arm's machine/atomic.h, fix the places
where atomic.h was being included without ensuring that types.h (via
param.h) was included first, as required by atomic(9).

Remove arm's cpuconf.h, and references to it, after moving a few lines from
it into pmap-v4.h where they are used. Other than those few lines of
support for different MMU types, nothing in cpuconf.h has been used in our
code for quite a while.
The file existed to set up a variety of symbols to describe the
architecture. Over the past few years we have converted all of our source
to use the new architecture symbols standardized by ARM Inc, and predefined
by both clang and gcc.

MFC r306262, r306267, r310021: (needed to avoid conflicts on later merges)

Remove bus_dma_get_range and bus_dma_get_range_nb on armv6. We only need
this on a few earlier arm SoCs.

Restrict where we need to define fdt_fixup_table to just PowerPC and
Marvell.

Add the missing void to function signatures in much of the arm code.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Start to clean MIDR values using the CPUID scheme. We don't need to know
the exact CPU we are running on to set the cpu functions. Relax the check
to ignore the CPU revision. Even so this may still be too specific.

Reviewed by: mmel
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D6504

Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.

ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.

Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.

Loves it: imp

Use the new(-ish) CP15_SCTLR macro to generate system control reg accesses
where possible. In the places that doesn't work (multi-line inline asm,
and places where the old armv4 cpufuncs mechanism is used), annotate the
accesses with a comment that includes SCTLR. Now a grep -i sctlr can find
all the system control register manipulations.

No functional changes.

The cpu_reset_needs_v4_MMU_disable variable is only used in locore-v4.S,
only define it when building for ARMv5 or prior.

Sponsored by: ABT Systems Ltd

ARM: For ARMv6/v7, code in locore.S initializes SCTLR and ACTRL registers.
Don't duplicate this initialization in cpu_setup().

ARM: Don't use ugly (and hidden) global variable, control register is
readable at any time.

ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent.
Remove it from cpu_functions table.

ARM: Remove support for xscale i80219 and i80321 CPUs. We haven't single
supported config/board with these CPUs.

ARM: All remaining functions in cpufunc_asm_arm10.S are identical with
functions in cpufunc_asm_arm9.S. Use arm9 variants and remove
cpufunc_asm_arm10.S completly.

ARM: Remove last unused function, cpu_flush_prefetchbuf(),
from cpu_functions table.

ARM: Rename remaining instances of cpufunc_id() to cpu_ident(),
forgotten in r295096.
Remove tlb_flushI/tlb_flushI_SE functions forgotten in r295122.

ARM: Remove never used cpu_tlb_flushI and cpu_tlb_flushI_SE() functions
and their implementations.

ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress
functions are equal for all ARM variants. Remove them from cpu_functions
table.

ARM: Next round of cpufunc.* cleaning. Nobody uses flush_brnchtgt* functions,
delete them.

ARM: First round of cpufunc.* cleaning. All abort_fixup functions are
not currently used or defined. Delete them.

Retire pmap_pte_init_mmu_v6() which was used by old pmap-v6.

ARM: Add support for new KRAIT 300 CPU revision.

Approved by: kib (mentor)

Set the correct values in the arm aux control register, based on chip type.

The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>

The Broadcom BCM56060 chip has a Cortex-A9R4 core.

Submitted by: Steve Kiernan <stevek@juniper.net>
Reviewed by: imp@
Differential Revision: https://reviews.freebsd.org/D3357

Remove trailing whitespace from sys/arm/arm

Add more cp15_ functions, and use them in cpufunc.c where possible.

It appears to be armv7_sleep is a duplication of armv7_cpu_sleep.
For consistency with the naming conventions used by the other
implementations kill armv7_sleep and keep armv7_cpu_sleep.

Differential Revision: https://reviews.freebsd.org/D2537
Submitted by: John Wehle
Reviewed by: ian@, andrew@

Delete cpu_do_powersave which is set but never used/tested
serving no useful purpose.

Differential Revision: https://reviews.freebsd.org/D2516
Submitted by: John Wehle
Reviewed by: ian@

Use ARMv7 style unaligned access on ARMv6. We set this bit in locore, but
it was missing from here.

Restore setting cpufuncs on arm1176, it was removed by accident with the
arm1136 code.

Reviewed by: ian

Remove support for CPU_XSCALE_80200. None of our configs support it, and
there wasn;t an option to enable it.

While here remove a check for CPU_ARM10 being defined as it has also been
removed.

Remove support for CPU_FA626TE. It's unused by any of our kernel configs.

Remove arm1136 support. We don't have any configs that use it, and I don't
expect us to add support for any more arm11 SoCs.

Remove the bootconfig parsing. We never used it and always passed either an
empty string or NULL to the setup functions that called into it.

Remove ARM9_CACHE_WRITE_THROUGH, none of our configs define it.

Remove support for CPU_ARM10. No kernel configs could possibly use this as
it's not an available option. Along with this we will never support this
cpu type as very few arm10 chips were made.

Resolve cache line size from CP15

Switch the cache line size during invalidations/flushes
to be read from CP15 cache type register.

Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: ian, imp
Obtained from: Semihalf

Correct cpu type, it was rather Cortex A12 R0.

Approved by: stas (mentor)

Add CPU ID for ARM Cortex A17.

Approved by: stas (mentor)

Different versions of the ARM processor use different registers.
Fix the code used on a Raspberry Pi.

Reviewed by: markm@

Fix context switch on PJ4Bv7 and remove obsolete pj4b_/arm11 functions

Use armv7_setttb that sets proper PT attributes.
Get rid of unused CPU functions, put nullop instead.
Exchange obsolete pj4b_/arm11_ functions to the appropriate armv7_ ones.

Give suitably-endowed ARMs a register similar to the x86 TSC register.

Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.

The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.

One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.

Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.

Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.

Reviewed by: ian@ (an earlier version)
Tested by: ian@ (same earlier version)
Committed from: WANDBOARD-QUAD

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.

Provide a proper armv7 implementation of icache_sync_all rather than
using armv7_idcache_wbinv_all, because wbinv_all doesn't broadcast the
operation to other cores. In elf_cpu_load_file() use icache_sync_all()
and explain why it's needed (and why other sync operations aren't).

As part of doing this, all callers of cpu_icache_sync_all() were
inspected to ensure they weren't relying on the old side effect of
doing a wbinv_all along with the icache work.

Add Cortex-A15 cpu id revisions.

Use armv7 TLB flush code, not arm11, for cortex-a processors.

The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware. That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation. On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.

Remove all traces of support for ARM chips prior to the arm9 series. We
never actually ran on these chips (other than using SA1 support in an
emulator to do the early porting to FreeBSD long long ago). The clutter
and complexity of some of this code keeps getting in the way of other
maintenance, so it's time to go.

Add an armv7 implementation of cpu_sleep(). The arm11/armv6 implementation
we've been using was actually just spinning due to ARM having redefined
the old 'wait for interrupt' operation via the system coprocessor as a nop
and replacing it with a WFI instruction.

Add a new cache maintenance function, idcache_inv_all, to the table, and
implementations for each of the chips we support. Most chips up through
armv6 can use the armv4 implementation which has a single coprocessor
opcode for this operation. The rather more complex armv7 implementation
comes from netbsd.

Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in
Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural
similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded
boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064.

Approved by: stas (mentor)

Remove not working and deprecated PJ4Bv6 support

Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.

Remove the last dregs of trapframe_t. It turns out only arm was using
this type, so remove it to make arm code more consistant with other
platforms. Thanks to bde@ for pointing out only arm used trapframe_t.

Add CPU ID for ARM Cortex A5.

Approved by: cognet (mentor)

Add identification for Cortex-A7 (R0) cores.

Reviewed by: cognet@

Add identification for Cortex-A15 (R0) cores.

Submitted by: Ruslan Bukin <br@bsdpad.com>

Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.

Submitted by: Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Tested by: wkoszek (ZedBoard)
Reviewed by: wkoszek, freebsd-arm@ (no objections raised)

Use armv7_drain_writebuf() and armv7_context_switch, instead of the arm11
variants.

Replace generic ARM11 option with more specific
support for ARM1136 and ARM1176

Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp>
Obtained from: NetBSD

Don't include arm/xscale/i8134x/i81342reg.h when we're compiling LINT.
The definitions in i81342reg.h clash with those in i80321reg.h.

Make it clear the L2 ops are filled for any cpu using a PL310 cache, not just
the omap4.

Spotted out by: Giovanni Trematerra <gianni at freebsd DOT org>

Use the arrmv7 version for flushID too, as it does something different for SMP.

Submitted by: Giovanni Trematerra <gianni at freebsd DOT org>

Support identification of new PJ4B cores.

Obtained from: Semihalf

Add support for ARM11 cpufunc

Obtained from: NetBSD (partially)

Merging projects/armv6, part 1

Cummulative patch of changes that are not vendor-specific:
- ARMv6 and ARMv7 architecture support
- ARM SMP support
- VFP/Neon support
- ARM Generic Interrupt Controller driver
- Simplification of startup code for all platforms

Final whitespace trim.

Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's
heatsink termperature in open air from 49C to 43C when idle.

Add support for FA626TE.
Tested on GM8181 development board.

Show the cpu info for fa526

Submitted by: Yohanes Nugroho <yohanes at gmail dot com>

Add support for Cavium Econa CNS11XX ARM boards. These boards were
previously know by StarSemi STR9104.

Tested by the submitter on an Emprex NSD-100 board.

Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...

Remove remaining bits of performance counter support.

Submitted by: Tom Judge <tom at tomjudge.com>

Remove performance counter headers. This code came from NetBSD, but our
hardware perf. counter support is different, so we don't need these
files.

Reviewed by: freebsd-arm (no comments)

Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.

On some ARM variations CPU func dispatcher has the D-cache invalidate method
point to write-back invalidate, which is wrong, and can lead to a crash/panic
on affected platforms.

Spotted by: HPS
Reviewed by: cognet
Approved by: re (kib)

- Add support for PXA270 cpu.

Submitted by: Jacques Fourie <jacques.fourie@gmail.com>

Fix confusing naming of Marvell ARM CPU specific routines.

- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.

- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.

This will be accompanied by a file rename commit.

Merge support for Gateworks Cambria boards:
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support

Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD

Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp

Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571.

They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from: Marvell, Semihalf

Fixes for ARM9/ARM10 :
Call uma_sel_align() there at well.
Set CPU_CONTROL_VECRELOC if we're using the high vectors page.

Submitted by: Rafal Jaworowski <raj AT semihalf DOT com>
MFC After: 1 week

Add entries for the L2 cache-related functions for armv5.

Spotted out by: Rafal Jaworowski

Don't define get_cachetype() for CPU_ARM9E unless it's going to be used.

Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.

Obtained from: NetBSD

Add cast to silent gcc warnings.

Approved by: re (blanket)

Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.

Approved by: re (blanket)

Use uma_set_align().

First bits of Xscale core 3 support (the VM bits are far from being optimal
yet).

Gateworks Avila board support:
o ixp425 support
o NPE network driver (requires Intel microcode)
o h/w qmgr support
o True IDE compact flash over expansion bus
o pci (ath and hifn795x parts tested)
o xscale watchdog timer
o ds1672 RTC on i2c bus
o ad7418 voltage + temp monitoring on i2c bus
o uart

Work done together with cognet, kevlo, and jmg. Parts of
the ixp425 support obtaine/derived from netbsd.

Reviewed by: cognet, imp
MFC after: 1 month

Identify the xscale 81342.

style(9) cleanup.

Approved by: cognet

Finally bring it support for the i80219 XScale processor.

Submitted by: Max M. Boyarov <m.boyarov bsd by>

MFp4: Use CPU_CONTROL_ROUNDROBIN for arm9, it seems to give marginally
better performances.

Remove bits specific to CPUs we won't support (< armv4).

MFp4: Setup arm9 to write back by default.

Obtained from: NetBSD

Support high vectors for arm9.

Obtained from: NetBSD

Start all license statements with /*-

Remove __P here too.

Ok'ed by: cognet

Call pmap_pte_init_arm9 instead of pmap_pte_init_generic if
ARM9_CACHE_WRITE_THROUGH is defined.

Use the right path for xscale files.

Uncomment the vector relocation code.

Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.