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336190 |
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11-Jul-2018 |
araujo |
MFC r335030:
Add SPDX tags to vmm(4).
Sponsored by: iXsystems Inc.
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330623 |
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07-Mar-2018 |
jhb |
MFC 328102: Save and restore guest debug registers.
Currently most of the debug registers are not saved and restored during VM transitions allowing guest and host debug register values to leak into the opposite context. One result is that hardware watchpoints do not work reliably within a guest under VT-x.
Due to differences in SVM and VT-x, slightly different approaches are used.
For VT-x:
- Enable debug register save/restore for VM entry/exit in the VMCS for DR7 and MSR_DEBUGCTL. - Explicitly save DR0-3,6 of the guest. - Explicitly save DR0-3,6-7, MSR_DEBUGCTL, and the trap flag from %rflags for the host. Note that because DR6 is "software" managed and not stored in the VMCS a kernel debugger which single steps through VM entry could corrupt the guest DR6 (since a single step trap taken after loading the guest DR6 could alter the DR6 register). To avoid this, explicitly disable single-stepping via the trace flag before loading the guest DR6. A determined debugger could still defeat this by setting a breakpoint after the guest DR6 was loaded and then single-stepping.
For SVM: - Enable debug register caching in the VMCB for DR6/DR7. - Explicitly save DR0-3 of the guest. - Explicitly save DR0-3,6-7, and MSR_DEBUGCTL for the host. Since SVM saves the guest DR6 in the VMCB, the race with single-stepping described for VT-x does not exist.
For both platforms, expose all of the guest DRx values via --get-drX and --set-drX flags to bhyvectl.
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302408 |
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07-Jul-2016 |
gjb |
Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle. Prune svn:mergeinfo from the new branch, as nothing has been merged here.
Additional commits post-branch will follow.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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282287 |
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30-Apr-2015 |
neel |
Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>.
Only a subset of source files that include <machine/vmm.h> need to use the APIs that require the inclusion of <sys/cpuset.h>.
MFC after: 1 week
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276402 |
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30-Dec-2014 |
neel |
Remove "svn:mergeinfo" property that was dragged along when these files were svn copied in r273375.
Suggested by: ngie, gjb
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273766 |
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28-Oct-2014 |
araujo |
Reported by: Coverity CID: 1249760 Reviewed by: neel Approved by: neel Sponsored by: QNAP Systems Inc.
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#
273375 |
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21-Oct-2014 |
neel |
Merge projects/bhyve_svm into HEAD.
After this change bhyve supports AMD processors with the SVM/AMD-V hardware extensions.
More details available here: https://lists.freebsd.org/pipermail/freebsd-virtualization/2014-October/002905.html
Submitted by: Anish Gupta (akgupt3@gmail.com) Tested by: Benjamin Perrault (ben.perrault@gmail.com) Tested by: Willem Jan Withagen (wjw@digiware.nl)
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272916 |
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10-Oct-2014 |
neel |
Fix bhyvectl so it works correctly on AMD/SVM hosts. Also, add command line options to display some key VMCB fields.
The set of valid options that can be passed to bhyvectl now depends on the processor type. AMD-specific options are identified by a "--vmcb" or "--avic" in the option name. Intel-specific options are identified by a "--vmcs" in the option name.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
271939 |
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21-Sep-2014 |
neel |
Allow more VMCB fields to be cached: - CR2 - CR0, CR3, CR4 and EFER - GDT/IDT base/limit fields - CS/DS/ES/SS selector/base/limit/attrib fields
The caching can be further restricted via the tunable 'hw.vmm.svm.vmcb_clean'.
Restructure the code such that the fields above are only modified in a single place. This makes it easy to invalidate the VMCB cache when any of these fields is modified.
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271346 |
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10-Sep-2014 |
neel |
Move the VMCB initialization into svm.c in preparation for changes to the interrupt injection logic.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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271345 |
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10-Sep-2014 |
neel |
Move the event injection function into svm.c and add KTR logging for every event injection.
This in in preparation for changes to SVM guest interrupt injection.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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271203 |
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06-Sep-2014 |
neel |
Do proper ASID management for guest vcpus.
Prior to this change an ASID was hard allocated to a guest and shared by all its vcpus. The meant that the number of VMs that could be created was limited to the number of ASIDs supported by the CPU. It was also inefficient because it forced a TLB flush on every VMRUN.
With this change the number of guests that can be created is independent of the number of available ASIDs. Also, the TLB is flushed only when a new ASID is allocated.
Discussed with: grehan Reviewed by: Anish Gupta (akgupt3@gmail.com)
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271152 |
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05-Sep-2014 |
neel |
Merge svm_set_vmcb() and svm_init_vmcb() into a single function that is called just once when a vcpu is initialized.
Discussed with: Anish Gupta (akgupt3@gmail.com)
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270511 |
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24-Aug-2014 |
neel |
An exception is allowed to be injected even if the vcpu is in an interrupt shadow, so move the check for pending exception before bailing out due to an interrupt shadow.
Change return type of 'vmcb_eventinject()' to a void and convert all error returns into KASSERTs.
Fix VMCB_EXITINTINFO_EC(x) and VMCB_EXITINTINFO_TYPE(x) to do the shift before masking the result.
Reviewed by: Anish Gupta (akgupt3@gmail.com)
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#
267217 |
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07-Jun-2014 |
grehan |
Set the guest PAT MSR in the VMCB to power-on defaults.
Linux guests accept the values in this register, while *BSD guests reprogram it. Default values of zero correspond to PAT_UNCACHEABLE, resulting in glacial performance.
Thanks to Willem Jan Withagen for first reporting this and helping out with the investigation.
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#
267096 |
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05-Jun-2014 |
grehan |
Allow the guest's CR2 value to be read/written. This is required for page-fault injection.
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#
267003 |
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03-Jun-2014 |
grehan |
Bring (almost) up-to-date with HEAD.
- use the new virtual APIC page - update to current bhyve APIs
Tested by Anish with multiple FreeBSD SMP VMs on a Phenom, and verified by myself with light FreeBSD VM testing on a Sempron 3850 APU.
The issues reported with Linux guests are very likely to still be here, but this sync eliminates the skew between the project branch and CURRENT, and should help to determine the causes.
Some follow-on commits will fix minor cosmetic issues.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
259579 |
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18-Dec-2013 |
grehan |
Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
249967 |
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27-Apr-2013 |
neel |
- SVM nested paging support - Define data structures to contain the SVM vcpu context - Define data structures to contain guest and host software context - Change license in vmcb.h and vmcb.c to remove references to NetApp that inadvertently sneaked in when the license text was copied from amdv.c.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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#
249493 |
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15-Apr-2013 |
neel |
Add a Cliff Notes version of the purpose and contents of the VMCB.
Requested by: julian
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#
249353 |
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11-Apr-2013 |
neel |
Provide functions to manipulate the guest state in the VMCB.
Submitted by: Anish Gupta (akgupt3@gmail.com)
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