- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1
builds.
- Update newvers.sh to reflect RC1.
- Update __FreeBSD_version to reflect 10.3.
- Update default pkg(8) configuration to use the quarterly branch.

Approved by: re (implicit)

MFC r263710, r273377, r273378, r273423 and r273455:

- De-vnet hash sizes and hash masks.
- Fix multiple issues related to arguments passed to SYSCTL macros.

Sponsored by: Mellanox Technologies

MFC: r258722, r258757

r258722:
Give some output about the CPU clock on IBMPOWER machines, currently read
from OF. Linux does it similar, means they also read the OF values and
display them.
r258757:
Use the Open Firmware-based CPU frequency determination as a generic
fallback if we can't measure CPU frequency. This is also useful on a
variety of embedded systems using FDT.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add POWER7+ and POWER8 to the CPU ID table.

Approved by: re (kib)

Add POWER CPUs to the kernel's knowledge. This does not imply we currently
actually run on any machines with POWER CPUs but avoids closing that door
unnecessarily.

Approved by: re (kib)

MFcalloutng:
When CPU becomes idle, cpu_idleclock() calculates time to the next timer
event in order to reprogram hw timer. Return that time in sbintime_t to
the caller and pass it to acpi_cpu_idle(), where it can be used as one
more factor (quite precise) to extimate furter sleep time and choose
optimal sleep state. This is a preparatory change for further callout
improvements will be committed in the next days.

The commmit is not targeted for MFC.

Let us manage differences of Book-E PowerPC variations i.e. vendor /
implementation specific vs. the common architecture definition.

Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under
BOOKE_PPC4XX are not used in the code yet.

This change set is not supposed to affect existing E500 support, it's just
another reorg step before bringing support for E500mc, E5500 and PPC465.

Obtained from: AppliedMicro, Freescale, Semihalf

Rename e500 prefix to match other Book-E CPU variations. CPU id tidbits for
the new cores.

Obtained from: Freescale, Semihalf.

Revert r225875, r225877:
It is reported that on some chips (e.g. the 970MP) behavior of POW bit set
simultaneously with modifying other bits is undefined and may cause hangs.
The race should be handled in some other way, but for now just get back.

Reported by: nwitehorn

Add header missed in r225875.

MFC after: 3 days

Handle the race in cpu_idle() when due to the critical section CPU could get
into sleep after receiving interrupt, delaying interrupt thread execution
indefinitely until the next interrupt arrive.

Reviewed by: nwhitehorn
MFC after: 3 days

Add CPU support code for the IBM Cell Broadband Engine.

Centralize CPU idle routines into powerpc/cpu.c and use the same
cpu_idle_hook mechanism that x86 uses for overriding the idle routine.
This is required for supporting ilding the CPU under PowerPC hypervisors.

Entering deep nap mode on the 970MP requires that both MSR[NAP] and
MSR[DEEPNAP] be set, not just MSR[DEEPNAP]. Fixing this reduces the idle
temperature of my CPUs from 57 to 38 degrees and makes one-shot timer
mode work properly.

Hint from: mav
MFC after: 4 days

MFppc64:

Kernel sources for 64-bit PowerPC, along with build-system changes to keep
32-bit kernels compiling (build system changes for 64-bit kernels are
coming later). Existing 32-bit PowerPC kernel configurations must be
updated after this change to specify their architecture.

Enable power management for E500 cores. Use "doze" for now to make
sure the caches remain coherent. For single-core configurations and
with busdma changes we could eventually switch to "nap" and force
a D-cache invalidation as part of the DMA completion. To this end,
clear PSL_WE until after we handled the decrementer or external
interrupt as it tells us whether we just woke up or not.

Turn on experimental support for DEEPNAP on the 970MP.

Add a CPU features framework on PowerPC and simplify CPU setup a little
more. This provides three new sysctls to user space:
hw.cpu_features - A bitmask of available CPU features
hw.floatingpoint - Whether or not there is hardware FP support
hw.altivec - Whether or not Altivec is available

PR: powerpc/139154
MFC after: 10 days

Fix cpuid output on E500 core.

Unbreak E500 builds. The inline assembly for the 970 CPUs
is invalid when compiling for BookE.

Turn on NAP mode on G5 systems, and refactor the HID0 setup code a little.
This makes my G5 Xserve sound slightly less like it is filled with
howling banshees.

Add SMP support on U3-based G5 systems. This does not yet work perfectly:
at least on my Xserve, getting the decrementer and timebase on APs to tick
requires setting up a clock chip over I2C, which is not yet done.

While here, correct the 64-bit tlbie function to set the CPU to 64-bit
mode correctly.

Hardware donated by: grehan

Teach cpu_est_clockrate() about the G5's slightly different PMC. This
allows the boot messages to include the CPU speed and makes possible
the forthcoming cpufreq support for the PPC 970.

Introduce support for cpufreq on PowerPC with the dynamic frequency
switching capabilities of the MPC7447A and MPC7448.

Eliminate redundant setting of HID0_EMCP.

Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode
provided, for example, on the PowerPC 970 (G5), as well as on related CPUs
like the POWER3 and POWER4.

This also adds support for various built-in hardware found on Apple G5
hardware (e.g. the IBM CPC925 northbridge).

Reviewed by: grehan

Unbreak support for G4s without an L3 cache. L3 cache support was introduced
with, and limited to, the Motorola/Freescale 745x family.

Reported by: Marco Trillo

Unbreak G3 support. G3 processors don't have an L3 cache, so we shouldn't try to program it.

Approved by: marcel (mentor)

Rename cpu_config_l2cr() to cpu_print_cacheinfo(). We're not
configuring the L2 cache on the BSP. Nor the L3 cache. We
merely print the settings.

Save the L2 and L3 cache configuration in global values so
that we know how to configure the cache on APs.

For AIM, have cpu_idle() set MSR_POW when the powerpc_pow_enabled
variable is set. On my Mac Mini this puts the CPU in NAP mode when
the kernel is idle and, any technical or environmental reasons
aside, avoids that I have to listen to the fan all day :-)

Teach PowerPC CPU identification routines to recognize e500 cores. Fix style
issues in this area.

Approved by: cognet (mentor)
MFp4: e500

The table of known CPU models ends with an entry that has a version
of 0, not with an entry that has an empty CPU name.

Submitted by: Andrew Turner (andrew@fubar.geek.nz)

Propagate the CPU model to the hw.model sysctl.

- recognize 7447A/7448 CPUs (used in miniMacs)
- enable 745x branch caches. Already enabled by OpenFirmware
on Macs, but reduces NetBSD diffs and usable by embedded folk.

Obtained from: NetBSD

/* -> /*- for license, minor formatting changes

Disable branch-target instruction cache on MPC7457 as outlined
in Motorola processor errata.

Submitted by: Suleiman Souhlal <refugee@segfaulted.com>

Recognize MPC7547 (aka G4+)

DELAY must be a routine, not a macro definition.

Export the ns_per_tick variable through md_var.h rather than by declaring
it extern in cpu.c.

Add cpu.c. This contains one exported function, cpu_setup(), which handles
setup of and printing information about cpus.

Obtained from: NetBSD (parts)