#
296373 |
|
04-Mar-2016 |
marius |
- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.3. - Update default pkg(8) configuration to use the quarterly branch.
Approved by: re (implicit) |
#
266003 |
|
14-May-2014 |
ian |
MFC r257995, r258244, r258246,
Rename the "bare" platform "mpc85xx" Also turn "bare" into a truly bare platform
Move CCSR discovery into the platform module
There is no reason Book-E needs to save XER and CTR on context switches.
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#
266001 |
|
14-May-2014 |
ian |
MFC r258002, r258024, r258027, r258051, r258052, r258243, r258244, r258002, r258024, r258027, r258051, r258052, r258243,
Follow up r223485, which made AIM use the ABI thread pointer instead of PCPU fields for curthread, by doing the same to Book-E.
Use the same implementation of copyinout.c for both AIM and Book-E.
Actually add IOMMU domain to the list of known mappings.
Following the approach with ACPI DMAR on x86, split IOMMU handling into a variant PCI bus instead of trying to shoehorn it into the PCI host bridge adapter.
Make sure that TLB1 mappings are aligned correctly.
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#
265996 |
|
14-May-2014 |
ian |
MFC r257161, r257169, r257178, r257190, r257191
Add pmap_mapdev_attr() and pmap_kenter_attr() interfaces.
Fix concurrency issues with TLB1 updates and make pmap_kextract() search TLB1 mappings as well
Interrelated improvements to early boot mappings: - Remove explicit requirement that the SOC registers be found except as an optimization (although the MPC85XX LAW drivers still require they be found externally, which should change). - Remove magic CCSRBAR_VA value. - Allow bus_machdep.c's early-boot code to handle non 1:1 mappings and systems not in real-mode or global 1:1 maps in early boot. - Allow pmap_mapdev() on Book-E to reissue previous addresses if the area is already mapped. Additionally have it check all mappings, not just the CCSR area.
Add some extra sanity checking and checks to printf format specifiers.
Bump initial TLB size. The kernel is not necessarily less than 16 MB
Handle (in a slightly ugly way) ePAPR-type loaders that just place a device tree into r3.
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#
265954 |
|
13-May-2014 |
ian |
MFC r256814, r256816, r256818, r256846, r256855, r256864 (by nwhitehorn):
- Handle 2GB of ram - Allow the OFW interrupt mapping code to work with PCI devices not enumerated by Open Firmware, as in the case of FDT. - Provide an interface for PCI bus drivers that need some of ofw_pci's metadata during attach. - Use standard ofw_bus helpers instead of reinventing the wheel. - Make hard-wired TLB allocations be at minimum one page.
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#
256281 |
|
10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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#
248084 |
|
09-Mar-2013 |
attilio |
Switch the vm_object mutex to be a rwlock. This will enable in the future further optimizations where the vm_object lock will be held in read mode most of the time the page cache resident pool of pages are accessed for reading purposes.
The change is mostly mechanical but few notes are reported: * The KPI changes as follow: - VM_OBJECT_LOCK() -> VM_OBJECT_WLOCK() - VM_OBJECT_TRYLOCK() -> VM_OBJECT_TRYWLOCK() - VM_OBJECT_UNLOCK() -> VM_OBJECT_WUNLOCK() - VM_OBJECT_LOCK_ASSERT(MA_OWNED) -> VM_OBJECT_ASSERT_WLOCKED() (in order to avoid visibility of implementation details) - The read-mode operations are added: VM_OBJECT_RLOCK(), VM_OBJECT_TRYRLOCK(), VM_OBJECT_RUNLOCK(), VM_OBJECT_ASSERT_RLOCKED(), VM_OBJECT_ASSERT_LOCKED() * The vm/vm_pager.h namespace pollution avoidance (forcing requiring sys/mutex.h in consumers directly to cater its inlining functions using VM_OBJECT_LOCK()) imposes that all the vm/vm_pager.h consumers now must include also sys/rwlock.h. * zfs requires a quite convoluted fix to include FreeBSD rwlocks into the compat layer because the name clash between FreeBSD and solaris versions must be avoided. At this purpose zfs redefines the vm_object locking functions directly, isolating the FreeBSD components in specific compat stubs.
The KPI results heavilly broken by this commit. Thirdy part ports must be updated accordingly (I can think off-hand of VirtualBox, for example).
Sponsored by: EMC / Isilon storage division Reviewed by: jeff Reviewed by: pjd (ZFS specific review) Discussed with: alc Tested by: pho
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#
242526 |
|
03-Nov-2012 |
marcel |
1. Have the APs initialize the TLB1 entries from what has been programmed on the BSP during (early) boot. This makes sure that the APs get configured the same as the BSP, irrspective of how FreeBSD was loaded. 2. Make sure to flush the dcache after writing the TLB1 entries to the boot page. The APs aren't part of the coherency domain just yet. 3. Set pmap_bootstrapped after calling pmap_bootstrap(). The FDT code now maps the devices (like OF), and this resulted in a panic. 4. Since we pre-wire the CCSR, make sure not to map chunks of it in pmap_mapdev().
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#
238030 |
|
02-Jul-2012 |
marcel |
Implement cpu_flush_dcache(). This allows us to optimize __syncicache() for the common case in chich D-caches are coherent by virtue of busdma.
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#
236324 |
|
30-May-2012 |
raj |
Extract vendor specific Book-E pieces into separate files and have a common skeleton (maybe we should kobj-tize this one day).
Note the PPC4xx bit is not connected to the build yet.
Obtained from: AppliedMicro, Semihalf.
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#
236141 |
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27-May-2012 |
raj |
Let us manage differences of Book-E PowerPC variations i.e. vendor / implementation specific vs. the common architecture definition.
Bring PPC4XX defines (PSL, SPR, TLB). Note the new definitions under BOOKE_PPC4XX are not used in the code yet.
This change set is not supposed to affect existing E500 support, it's just another reorg step before bringing support for E500mc, E5500 and PPC465.
Obtained from: AppliedMicro, Freescale, Semihalf
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#
236097 |
|
26-May-2012 |
raj |
Rename e500 prefix to match other Book-E CPU variations. CPU id tidbits for the new cores.
Obtained from: Freescale, Semihalf.
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#
230767 |
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30-Jan-2012 |
kib |
Finally, try to enable the nxstacks on amd64 and powerpc64 for both 64bit and 32bit ABIs. Also try to enable nxstacks for PAE/i386 when supported, and some variants of powerpc32.
MFC after: 2 months (if ever)
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#
222400 |
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28-May-2011 |
marcel |
Better support different kernel hand-offs. When loaded directly from U-Boot, the kernel is passed a standard argc/argv pair. The Juniper loader passes the metadata pointer as the second argument and passes 0 in the first. The FreeBSD loader passes the metadata pointer in the first argument.
As such, have locore preserve the first 2 arguments in registers r30 & r31. Change e500_init() to accept these arguments. Don't pass global offsets (i.e. kernel_text and _end) as arguments to e500_init(). We can reference those directly.
Rename e500_init() to booke_init() now that we're changing the prototype.
In booke_init(), "decode" arg1 and arg2 to obtain the metadata pointer correctly. For the U-Boot case, clear SBSS and BSS and bank on having a static FDT for now. This allows loading the ELF kernel and jumping to the entry point without trampoline.
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#
217688 |
|
21-Jan-2011 |
pluknet |
Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.
Submitted by: perryh pluto.rain.com (previous version) Reviewed by: jhb Approved by: kib (mentor) Tested by: universe
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#
217523 |
|
17-Jan-2011 |
marcel |
Support booting non FDT-capable loaders: 1. Allow embedding the FDT into the kernel, just like PowerPC/book-E. 2. If the loader passes us a pointer to the bootinfo structure, save it and use it to fill in the gaps (e.g. bus frequencies, etc).
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#
215159 |
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12-Nov-2010 |
nwhitehorn |
Add some platform KOBJ extensions and continue integrating PowerPC hypervisor infrastructure support: - Fix coexistence of multiple platform modules in the same kernel - Allow platform modules to provide an SMP topology - PowerPC hypervisors limit the amount of memory accessible in real mode. Allow the platform modules to specify the maximum real-mode address, and modify the bits of the kernel that need to allocate real-mode-accessible buffers to respect this limits.
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#
215157 |
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12-Nov-2010 |
nwhitehorn |
Centralize CPU idle routines into powerpc/cpu.c and use the same cpu_idle_hook mechanism that x86 uses for overriding the idle routine. This is required for supporting ilding the CPU under PowerPC hypervisors.
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#
215119 |
|
11-Nov-2010 |
raj |
Use local TLB_UNLOCKED marker instead of MTX_UNOWNED for Book-E PowerPC trap routines.
This unbreaks Book-E build after the recent machine/mutex.h removal.
While there move tlb_*lock() prototypes to machine/tlb.h.
Submitted by: jhb
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#
214835 |
|
05-Nov-2010 |
jhb |
Adjust the order of operations in spinlock_enter() and spinlock_exit() to work properly with single-stepping in a kernel debugger. Specifically, these routines have always disabled interrupts before increasing the nesting count and restored the prior state of interrupts after decreasing the nesting count to avoid problems with a nested interrupt not disabling interrupts when acquiring a spin lock. However, trap interrupts for single-stepping can still occur even when interrupts are disabled. Now the saved state of interrupts is not saved in the thread until after interrupts have been disabled and the nesting count has been increased. Similarly, the saved state from the thread cannot be read once the nesting count has been decreased to zero. To fix this, use temporary variables to store interrupt state and shuffle it between the thread's MD area and the appropriate registers.
In cooperation with: bde MFC after: 1 month
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#
212541 |
|
13-Sep-2010 |
mav |
Refactor timer management code with priority to one-shot operation mode. The main goal of this is to generate timer interrupts only when there is some work to do. When CPU is busy interrupts are generating at full rate of hz + stathz to fullfill scheduler and timekeeping requirements. But when CPU is idle, only minimum set of interrupts (down to 8 interrupts per second per CPU now), needed to handle scheduled callouts is executed. This allows significantly increase idle CPU sleep time, increasing effect of static power-saving technologies. Also it should reduce host CPU load on virtualized systems, when guest system is idle.
There is set of tunables, also available as writable sysctls, allowing to control wanted event timer subsystem behavior: kern.eventtimer.timer - allows to choose event timer hardware to use. On x86 there is up to 4 different kinds of timers. Depending on whether chosen timer is per-CPU, behavior of other options slightly differs. kern.eventtimer.periodic - allows to choose periodic and one-shot operation mode. In periodic mode, current timer hardware taken as the only source of time for time events. This mode is quite alike to previous kernel behavior. One-shot mode instead uses currently selected time counter hardware to schedule all needed events one by one and program timer to generate interrupt exactly in specified time. Default value depends of chosen timer capabilities, but one-shot mode is preferred, until other is forced by user or hardware. kern.eventtimer.singlemul - in periodic mode specifies how much times higher timer frequency should be, to not strictly alias hardclock() and statclock() events. Default values are 2 and 4, but could be reduced to 1 if extra interrupts are unwanted. kern.eventtimer.idletick - makes each CPU to receive every timer interrupt independently of whether they busy or not. By default this options is disabled. If chosen timer is per-CPU and runs in periodic mode, this option has no effect - all interrupts are generating.
As soon as this patch modifies cpu_idle() on some platforms, I have also refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions (if supported) under high sleep/wakeup rate, as fast alternative to other methods. It allows SMP scheduler to wake up sleeping CPUs much faster without using IPI, significantly increasing performance on some highly task-switching loads.
Tested by: many (on i386, amd64, sparc64 and powerc) H/W donated by: Gheorghe Ardelean Sponsored by: iXsystems, Inc.
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#
210247 |
|
19-Jul-2010 |
raj |
Eliminate FDT_IMMR_VA define.
This removes platform dependencies from <machine>/fdt.h for the benfit of portability.
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#
209975 |
|
13-Jul-2010 |
nwhitehorn |
MFppc64:
Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
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#
209950 |
|
12-Jul-2010 |
nwhitehorn |
Unify ABI-related bits of the Book-E and AIM machdep routines (exec_setregs, etc.) in order to simplify the addition of 64-bit support, and possible future extension of the Book-E code to handle hard floating point and Altivec.
MFC after: 1 month
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#
209908 |
|
11-Jul-2010 |
raj |
Convert Freescale PowerPC platforms to FDT convention.
The following systems are affected:
- MPC8555CDS - MPC8572DS
This overhaul covers the following major changes:
- All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values).
- This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI.
- Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data.
Note that world for these platforms has to be built WITH_FDT.
Reviewed by: imp Sponsored by: The FreeBSD Foundation
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#
209613 |
|
30-Jun-2010 |
jhb |
Move prototypes for kern_sigtimedwait() and kern_sigprocmask() to <sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
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#
205642 |
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25-Mar-2010 |
nwhitehorn |
Change the arguments of exec_setregs() so that it receives a pointer to the image_params struct instead of several members of that struct individually. This makes it easier to expand its arguments in the future without touching all platforms.
Reviewed by: jhb
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#
205527 |
|
23-Mar-2010 |
marcel |
Enable power management for E500 cores. Use "doze" for now to make sure the caches remain coherent. For single-core configurations and with busdma changes we could eventually switch to "nap" and force a D-cache invalidation as part of the DMA completion. To this end, clear PSL_WE until after we handled the decrementer or external interrupt as it tells us whether we just woke up or not.
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#
203924 |
|
15-Feb-2010 |
raj |
Call the proper linkup routine in PowerPC Book-E machdep.
Submitted by: attilio MFC after: 1 week
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#
199886 |
|
28-Nov-2009 |
nwhitehorn |
Add a CPU features framework on PowerPC and simplify CPU setup a little more. This provides three new sysctls to user space: hw.cpu_features - A bitmask of available CPU features hw.floatingpoint - Whether or not there is hardware FP support hw.altivec - Whether or not Altivec is available
PR: powerpc/139154 MFC after: 10 days
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#
198507 |
|
27-Oct-2009 |
kib |
In r197963, a race with thread being selected for signal delivery while in kernel mode, and later changing signal mask to block the signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls.
Use kern_sigprocmask() instead of direct manipulation of td_sigmask to reschedule newly blocked signals, closing the race.
Reviewed by: davidxu Tested by: pho MFC after: 1 month
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#
193156 |
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31-May-2009 |
nwhitehorn |
Introduce support for cpufreq on PowerPC with the dynamic frequency switching capabilities of the MPC7447A and MPC7448.
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#
192532 |
|
21-May-2009 |
raj |
Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.
Obtained from: Freescale, Semihalf
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#
192323 |
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18-May-2009 |
marcel |
Add cpu_flush_dcache() for use after non-DMA based I/O so that a possible future I-cache coherency operation can succeed. On ARM for example the L1 cache can be (is) virtually mapped, which means that any I/O that uses temporary mappings will not see the I-cache made coherent. On ia64 a similar behaviour has been observed. By flushing the D-cache, execution of binaries backed by md(4) and/or NFS work reliably. For Book-E (powerpc), execution over NFS exhibits SIGILL once in a while as well, though cpu_flush_dcache() hasn't been implemented yet.
Doing an explicit D-cache flush as part of the non-DMA based I/O read operation eliminates the need to do it as part of the I-cache coherency operation itself and as such avoids pessimizing the DMA-based I/O read operations for which D-cache are already flushed/invalidated. It also allows future optimizations whereby the bcopy() followed by the D-cache flush can be integrated in a single operation, which could be implemented using on-chips DMA engines, by-passing the D-cache altogether.
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#
192067 |
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14-May-2009 |
nwhitehorn |
Factor out platform dependent things unrelated to device drivers into a new platform module. These are probed in early boot, and have the responsibility of determining the layout of physical memory, determining the CPU timebase frequency, and handling the zoo of SMP mechanisms found on PowerPC.
Reviewed by: marcel, raj Book-E parts by: raj
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#
191362 |
|
21-Apr-2009 |
marcel |
o Properly set ksym_start & ksym_end when options DDB is set. Include opt_ddb.h for that. Now you can actually boot with -d and set breakpoints using function names. o Make sure to include opt_msgbuf.h. o Carve out the first 1MB of physical memory. The MPC85xx has DMA problems with addresses below 1MB. Ideally busdma knows how to avoid allocating below 1MB for MPC85xx, but that requires a bit more work. For now, ignore the 1MB of DRAM.
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#
190681 |
|
04-Apr-2009 |
nwhitehorn |
Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4.
This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge).
Reviewed by: grehan
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#
189100 |
|
27-Feb-2009 |
raj |
Make Book-E debug register state part of the PCB context.
Previously, DBCR0 flags were set "globally", but this leads to problems because Book-E fine grained debug settings work only in conjuction with the debug master enable bit in MSR: in scenarios when the DBCR0 was set with intention to debug one process, but another one with MSR[DE] set got scheduled, the latter would immediately cause debug exceptions to occur upon execution of its own code instructions (and not the one intended for debugging).
To avoid such problems and properly handle debugging context, DBCR0 state should be managed individually per process.
Submitted by: Grzegorz Bernacki gjb ! semihalf dot com Reviewed by: marcel
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#
187149 |
|
13-Jan-2009 |
raj |
Rework BookE pmap towards multi-core support.
o Eliminate tlb0[] (a s/w copy of TLB0) - The table contents cannot be maintained reliably in multiple MMU environments, where asynchronous events (invalidations from other cores) can change our local TLB0 contents underneath. - Simplify and optimize TLB flushing: system wide invalidations are performed using tlbivax instruction (propagates to other cores), for local MMU invalidations a new optimized routine (assembly) is introduced.
o Improve and simplify TID allocation and management. - Let each core keep track of its TID allocations. - Simplify TID recycling, eliminate dead code. - Drop the now unused powerpc/booke/support.S file.
o Improve page tables management logic.
o Simplify TLB1 manipulation routines.
o Other improvements and polishing.
Obtained from: Freescale, Semihalf
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#
186347 |
|
20-Dec-2008 |
nwhitehorn |
Modularize the Open Firmware client interface to allow run-time switching of OFW access semantics, in order to allow future support for real-mode OF access and flattened device frees. OF client interface modules are implemented using KOBJ, in a similar way to the PPC PMAP modules.
Because we need Open Firmware to be available before mutexes can be used on sparc64, changes are also included to allow KOBJ to be used very early in the boot process by only using the mutex once we know it has been initialized.
Reviewed by: marius, grehan
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#
186228 |
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17-Dec-2008 |
raj |
Minor clean up of BookE/MPC85XX: iprove naming and style(9).
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#
183319 |
|
24-Sep-2008 |
nwhitehorn |
Allow the cacheline size on PowerPC to be set at runtime. This is essential for supporting 64-bit CPUs, which often have 128-byte cache lines instead of the standard 32.
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#
182198 |
|
26-Aug-2008 |
raj |
Improve kernel stack handling on e500.
- Allocate thread0.td_kstack in pmap_bootstrap(), provide guard page - Switch to thread0.td_kstack as soon as possible i.e. right after return from e500_init() and before mi_startup() happens - Clean up temp stack area - Other minor cosmetics in machdep.c
Obtained from: Semihalf
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#
179229 |
|
23-May-2008 |
alc |
The VM system no longer uses setPQL2(). Remove it and its helpers.
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#
178471 |
|
25-Apr-2008 |
jeff |
- Add an integer argument to idle to indicate how likely we are to wake from idle over the next tick. - Add a new MD routine, cpu_wake_idle() to wakeup idle threads who are suspended in cpu specific states. This function can fail and cause the scheduler to fall back to another mechanism (ipi). - Implement support for mwait in cpu_idle() on i386/amd64 machines that support it. mwait is a higher performance way to synchronize cpus as compared to hlt & ipis. - Allow selecting the idle routine by name via sysctl machdep.idle. This replaces machdep.cpu_idle_hlt. Only idle routines supported by the current machine are permitted.
Sponsored by: Nokia
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#
177253 |
|
16-Mar-2008 |
rwatson |
In keeping with style(9)'s recommendations on macros, use a ';' after each SYSINIT() macro invocation. This makes a number of lightweight C parsers much happier with the FreeBSD kernel source, including cflow's prcc and lxr.
MFC after: 1 month Discussed with: imp, rink
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#
177110 |
|
12-Mar-2008 |
raj |
Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on what might be currently programmed into the registers.
Underlying firmware (U-Boot) would typically program MAC address into the first unit only, and others are left uninitialized. It is now possible to retrieve and program MAC address for all units properly, provided they were passed on in the bootinfo metadata.
Reviewed by: imp, marcel Approved by: cognet (mentor)
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#
176928 |
|
08-Mar-2008 |
marcel |
Enable the D-cache and I-cache when not already enabled. It so happens that U-Boot disables the D-cache when booting an ELF image, so this change makes sure we run with the D-cache enabled from now on. It shows too...
While here, remove the duplicate definition of the hw.model sysctl.
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#
176771 |
|
03-Mar-2008 |
raj |
Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.
The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E
This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555.
The following major integrated peripherals are supported:
* On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality)
This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base.
Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
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