- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1
builds.
- Update newvers.sh to reflect RC1.
- Update __FreeBSD_version to reflect 10.3.
- Update default pkg(8) configuration to use the quarterly branch.

Approved by: re (implicit)

MFC r264601,264646,265766,267918,267919,267920:

Merge if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded
CPU Ethernet Core.

The current version operates on a simple PIO based interface connected
to a NetFPGA-10G port.

To avoid confusion: this driver operates on a CPU running on the FPGA,
e.g. BERI/mips, and is not suited for the PCI host interface.

Adjust the register layout to allow for 64bit registers in the
future for nf10bmac(4). Also, add support for and enable RX interrupts.

Allow switching between 32bit and 64bit bus width data access at compile
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.

Adjust comments to indicate the 32 or 64bit register widths.

Relnotes: yes
Sponsored by: DARPA/AFRL

MFC r261351, r261352, r261355, r261396, r261397, r261398, r261403, r261404,
r261405

Open Firmware interrupt specifiers can consist of arbitrary-length byte
strings and include arbitrary information (IRQ line/domain/sense). When the
ofw_bus_map_intr() API was introduced, it assumed that, as on most systems,
these were either 1 cell, containing an interrupt line, or 2, containing
a line number plus a sense code. It turns out a non-negligible number of
ARM systems use 3 (or even 4!) cells for interrupts, so make this more
general.

Provide a simpler and more standards-compliant simplebus implementation to
get the Routerboard 800 up and running with the vendor device tree. This
does not implement some BERI-specific features (which hopefully won't be
necessary soon), so move the old code to mips/beri, with a higher attach
priority when built, until MIPS interrupt domain support is rearranged.

Allow nesting of simplebuses.

Add a set of helpers (ofw_bus_get_status() and ofw_bus_status_okay()) to
process "status" properties of OF nodes.

Fix one remnant endian flaw in nexus.

MFC r256911, r256936

MFP4: 223121 (PIC portion), 225861, 227822, 229692 (PIC only), 229693,
230523, 1123614

Implement a driver for Robert Norton's PIC as an FDT interrupt
controller. Devices whose interrupt-parent property points to a beripic

device will have their interrupt allocation, activation, and setup
operations routed through the IC rather than down the traditional bus
hierarchy.

This driver largely abstracts the underlying CPU away allowing the
PIC to be implemented on CPU's other than BERI. Due to insufficient
abstractions a small amount of MIPS specific code is currently required
in fdt_mips.c and to implement counters.

Sponsored by: DARPA/AFRL
Approved by: re (gjb)

MFC r256752, r256946

MFP4: 221483, 221567, 221568, 221670, 221677, 221678, 221800, 221801,
221804, 221805, 222004, 222006, 222055, 222820, 1135077, 1135118,
1136259

Add atse(4), a driver for the Altera Triple Speed Ethernet MegaCore.

The current driver support gigabit Ethernet speeds only and works with
the MegaCore only in the internal FIFO configuration in the soon to be
open sourced BERI CPU configuration.

MFP4: 1187103, 222076, 222057, 222051, 221799

Add atsectl, a simple utility to read and update MAC addresses stored in

the default flash location on Altera DE4 boards. Typically used once
when setting up a board so leaving in tools rather than inflicting on
all users.

To build with world add LOCAL_DIRS=tools/tools/atsectl to the make
command line.

Submitted by: bz
Sponsored by: DARPA/AFRL
Approved by: re (glebius)

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Partially merge Perforce changeset 219938 to head:

Write FDT attachment for the Terasic MTL (multitouch LCD) driver.
Exploit the fact that FDT allows multiple memory ranges to be
assigned to a device, giving us a cleaner description than
device.hints does.

Portions of this changeset that remove mtl from BERI device.hints and
add to DTS will be merged separately.

Sponsored by: DARPA, AFRL

Merge Perforce changeset 219922 to head:

Update nexus parts in copied DE4LED attachment to use FDT.

Sponsored by: DARPA, AFRL

Merge Perforce changeset 219918 to head:

Naive first cut at an FDT bus attachment for the Altera JTAG UART.

Sponsored by: DARPA, AFRL

Add terasic_de4led, a led(4) driver for the on-board 8-element LED on the
Terasic DE-4 board. Allow LED configuration to be set using loader
tunables, not just from userspace, and preconfigure LED 8 as a kernel
heartbeat. For now, this is a Nexus-attached, BERI-only driver, but it
could be used with other hard and soft cores on Altera FPGAs as well, in
principle.

Sponsored by: DARPA, AFRL

Add terasic_mtl(4), a device driver for the Terasic Multi-Touch LCD,
used with Terasic's DE-4 and other similar FPGA boards. This display
is 800x480 and includes a capacitive touch screen, multi-touch
gesture recognition, etc. This device driver depends on a Cambridge-
provided IP core that allows the MTL device to be hooked up to the
Altera Avalon SoC bus, and also provides a VGA-like text frame buffer.

Although it is compiled as a single device driver, it actually
implements a number of different device nodes exporting various
aspects of this multi-function device to userspace:

- Simple memory-mapped driver for the MTL 24-bit pixel frame buffer.
- Simple memory-mapped driver for the MTL control register set.
- Simple memory-mapped driver for the MTL text frame buffer.
- syscons attachment for the MTL text frame buffer.

This driver attaches directly to Nexus as is common for SoC device
drivers, and for the time being is considered BERI-specific, although
in principle it might be used with other hard and soft cores on
Altera FPGAs.

Control registers, including touchscreen input, are simply memory
mapped; in the future it would be desirable to hook up a more
conventional device node that can stream events, support kqueue(2)/
poll(2)/select(2), etc.

This is the first use of syscons on MIPS, as far as I can tell, and
there are some loose ends, such as an inability to use the hardware
cursor. More fundamentally, it appears that syscons(4) assumes that
either a host is PC-like (i386, amd64) *or* it must be using a
graphical frame buffer. While the MTL supports a graphical frame
buffer, using the text frame buffer is preferable for console use.
Fixing this issue in syscons(4) requires non-trivial changes, as the
text frame buffer support assumes that direct memory access can be
done to the text frame buffer without using bus accessor methods,
which is not the case on MIPS. As a workaround for this, we instead
double-buffer and pretend to be a graphical frame buffer exposing
text accessor methods, leading to some quirks in syscons behaviour.

Sponsored by: DARPA, AFRL

Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core,
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG. This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores. As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints. UART instances appear in /dev
as ttyu0, ttyu1, etc.

However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues. We work around
these as best we can, using various heuristics.

While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.

Sponsored by: DARPA, AFRL

Add preliminary support for the SRI International / University of Cambridge
Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.

Sponsored by: DARPA, AFRL