#
234906 |
|
02-May-2012 |
adrian |
MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII. + arge0 supports all four (two for non-Gige interfaces.) + arge1 only supports two (one for non-gige interfaces.) * Set the MII clock speed when changing the MAC PLL speed. + Needed for AR91xx and AR71xx; not needed for AR724x.
Tested:
* AR71xx only, I'll do AR913x testing tonight and fix whichever issues creep up.
TODO:
* Implement the missing AR7242 arge0 PLL configuration, but don't adjust the MII speed accordingly. * .. the AR7240/AR7241 don't require this, so make sure it's not set accidentally.
Bugs (not fixed here):
* Statically configured arge speeds are still broken - investigate why that is on the AP96 board. Autonegotiate is working fine, but there still seems to be an occasionally heavy packet loss issue.
Obtained from: Linux/Atheros/OpenWRT
|
#
211476 |
|
19-Aug-2010 |
adrian |
Preparation work for supporting the AR91xx and AR724x.
* Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others.
* Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits.
Reviewed by: imp@ Obtained from: (partially) Linux
|