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239671 |
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25-Aug-2012 |
rwatson |
Add preliminary support for the SRI International / University of Cambridge Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs, and is being used for CPU and OS research at several institutions.
Sponsored by: DARPA, AFRL
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