- Copy stable/10@285827 to releng/10.2 in preparation for 10.2-RC1
builds.
- Update newvers.sh to reflect RC1.
- Update __FreeBSD_version to reflect 10.2.
- Update default pkg(8) configuration to use the quarterly branch.[1]

Discussed with: re, portmgr [1]
Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC r279810, r279811:

Clean data cache before instruction cache in armv7_icache_sync_range().

Add minimum cache line sizes to struct cpuinfo, use them in the new cache
maintenance routines. Also add a routine to invalidate the branch cache.

MFC r276803, r276808:

Add accessors for the ARM CP15 performance monitor registers.
Move the inclusion of cpu-v6.h inside the #ifdef _KERNEL block.

MFC r276247, r276333, r276334, r276335, r276336, r276340, r276350:

Include acle-compat.h directly rather than getting it via sysreg.h.

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7.

Add new TLB and cache maintainence functions for armv6 and armv7.

Eliminate an unused macro whose name clashes now with a function in the
new cpu-v6.h

Add cache maintenance functions which will be used by startup code to
initially set up the MMU.

Fix a "decl is not a prototype" error noticed by gcc (but not clang).

Update comments (r4 is not used anywhere), use non-profiling entry macros.

Add arm option ARM_NEW_PMAP, to allow us to begin adding the new pmap
code alongside the existing implementation

Add armv6 implementations of cache operations to avoid duplication

Add new code to read and parse cpu identification data using the new CPUID
mechanism defined for armv7 (and also present on some armv6 chips including
the arm1176 used on rpi). The information is parsed into a global cpuinfo
structure, which will be used by (upcoming) new cache and tlb maintenance
code to handle cpu-specific variations of the maintence sequences.

Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz