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285830 |
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23-Jul-2015 |
gjb |
- Copy stable/10@285827 to releng/10.2 in preparation for 10.2-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.2. - Update default pkg(8) configuration to use the quarterly branch.[1]
Discussed with: re, portmgr [1] Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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268157 |
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02-Jul-2014 |
kib |
MFC r267651 (by attilio): Add the possibility to specify ecx when performing cpuid calls.
MFC r267673: Restore the ABI of the cpuctl(4) ioctl request CPUCTL_CPUID.
MFC r267814: Make cpuctl_do_cpuid() and cpuctl_do_cpuid_count() return void.
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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235317 |
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12-May-2012 |
gjb |
General mdoc(7) and typo fixes.
PR: 167776 Submitted by: Nobuyuki Koganemaru (kogane!jp.freebsd.org) MFC after: 3 days
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213573 |
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08-Oct-2010 |
uqs |
mdoc: drop redundant .Pp and .LP calls
They have no effect when coming in pairs, or before .Bl/.Bd
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208027 |
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13-May-2010 |
uqs |
mdoc: move CAVEATS, BUGS and SECURITY CONSIDERATIONS sections to the bottom of the manpages and order them consistently.
GNU groff doesn't care about the ordering, and doesn't even mention CAVEATS and SECURITY CONSIDERATIONS as common sections and where to put them.
Found by: mdocml lint run Reviewed by: ru
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195189 |
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30-Jun-2009 |
stas |
- Add support to atomically set/clear individual bits of a MSR register via cpuctl(4) driver. Two new CPUCTL_MSRSBIT and CPUCTL_MSRCBIT ioctl(2) calls treat the data field of the argument struct passed as a mask and set/clear bits of the MSR register according to the mask value. - Allow user to perform atomic bitwise AND and OR operaions on MSR registers via cpucontrol(8) utility. Two new operations ("&=" and "|=") have been added. The first one applies bitwise AND operaion between the current contents of the MSR register and the mask, and the second performs bitwise OR. The argument can be optionally prefixed with "~" inversion operator. This allows one to mimic the "clear bit" behavior by using the command like this: cpucontrol -m 0x10&=~0x02 # clear the second bit of TSC MSR
Inversion operator support in all modes (assignment, OR, AND).
Approved by: re (kib) MFC after: 1 month
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191414 |
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23-Apr-2009 |
brueffer |
Correct the information about when the respective functionality first appeared in FreeBSD.
PR: 133785 Submitted by: Ulrich Spoerlein <uqs@spoerlein.net> MFC after: 3 days
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186793 |
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05-Jan-2009 |
brueffer |
More wording improvements.
Discussed with: stas
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186739 |
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04-Jan-2009 |
stas |
- Improve wording.
Approved by: kib (mentor) MFC after: 1 week
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186614 |
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30-Dec-2008 |
brueffer |
Add missing comma.
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186613 |
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30-Dec-2008 |
brueffer |
Mdoc and wording improvements, also point to cpucontrol(8).
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181430 |
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08-Aug-2008 |
stas |
- Add cpuctl(4) pseudo-device driver to provide access to some low-level features of CPUs like reading/writing machine-specific registers, retrieving cpuid data, and updating microcode. - Add cpucontrol(8) utility, that provides userland access to the features of cpuctl(4). - Add subsequent manpages.
The cpuctl(4) device operates as follows. The pseudo-device node cpuctlX is created for each cpu present in the systems. The pseudo-device minor number corresponds to the cpu number in the system. The cpuctl(4) pseudo- device allows a number of ioctl to be preformed, namely RDMSR/WRMSR/CPUID and UPDATE. The first pair alows the caller to read/write machine-specific registers from the correspondent CPU. cpuid data could be retrieved using the CPUID call, and microcode updates are applied via UPDATE.
The permissions are inforced based on the pseudo-device file permissions. RDMSR/CPUID will be allowed when the caller has read access to the device node, while WRMSR/UPDATE will be granted only when the node is opened for writing. There're also a number of priv(9) checks.
The cpucontrol(8) utility is intened to provide userland access to the cpuctl(4) device features. The utility also allows one to apply cpu microcode updates.
Currently only Intel and AMD cpus are supported and were tested.
Approved by: kib Reviewed by: rpaulo, cokane, Peter Jeremy MFC after: 1 month
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