Copy stable/10@r272459 to releng/10.1 as part of
the 10.1-RELEASE process.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

MFC r258779,r258780,r258787,r258822:

Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit. Instead use (1U << 31) which gets the
expected result.

Similar to the (1 << 31) case it is not defined to do (2 << 30).

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Replace kernel virtual address space allocation with vmem. This provides
transparent layering and better fragmentation.

- Normalize functions that allocate memory to use kmem_*
- Those that allocate address space are named kva_*
- Those that operate on maps are named kmap_*
- Implement recursive allocation handling for kmem_arena in vmem.

Reviewed by: alc
Tested by: pho
Sponsored by: EMC / Isilon Storage Division

Remove duplicate code. Reduce diff between amd64 and i386.

Use volatile keywords properly.

Tidy up inline assembly. No functional change.

pciereg_cfg*: use assembly to access the mem-mapped cfg space

AMD BKDG for CPU families 10h and later requires that the memory
mapped config is always read into or written from al/ax/eax register.

Discussed with: kib, alc
Reviewed by: kib (earlier version)
MFC after: 25 days

On multi-core, multi-threaded PPC systems, it is important that the threads
be brought up in the order they are enumerated in the device tree (in
particular, that thread 0 on each core be brought up first). The SLIST
through which we loop to start the CPUs has all of its entries added with
SLIST_INSERT_HEAD(), which means it is in reverse order of enumeration
and so AP startup would always fail in such situations (causing a machine
check or RTAS failure). Fix this by changing the SLIST into an STAILQ,
and inserting new CPUs at the end.

Reviewed by: jhb

number of cleanups in i386 and amd64 pci md code

o introduce PCIE_REGMAX and use it instead of ad-hoc constant
o where 'reg' parameter/variable is not already unsigned, cast it to
unsigned before comparison with maximum value to cut off negative
values
o use PCI_SLOTMAX in several places where 31 or 32 were explicitly used
o drop redundant check of 'bytes' in i386 pciereg_cfgread() - valid
values are already checked in the subsequent switch

Reviewed by: jhb
MFC after: 1 week

Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.

MFC after: 1 week

Fall back to using configuration type 1 accesses for PCI config requests if
the requested PCI bus falls outside of the bus range given in the ACPI
MCFG table. Several BIOSes seem to not include all of the PCI busses in
systems in their MCFG tables. It maybe that the BIOS is simply buggy and
does support all the busses, but it is more conservative to just fall back
to the old method unless it is certain that memory accesses will work.

Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mapped
PCI config access.

Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe
memory-mapped config access. Add a workaround for these systems by
checking the first function of each slot on bus 0 using both the
memory-mapped config access and the older type 1 I/O port config access.
If we find a slot that is only visible via the type 1 I/O port config
access, we flag that slot. Future PCI config transactions to flagged
slots on bus 0 use type 1 I/O port config access rather than memory mapped
config access.

Extend the support for PCI-e memory mapped configuration space access:
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the
rest of the kernel. It now also accepts parameters via function
arguments rather than global variables.
- Add a notion of minimum and maximum bus numbers and reject requests for
an out of range bus.
- Add more range checks on slot/func/reg/bytes parameters to the cfg reg
read/write routines. Don't panic on any invalid parameters, just fail
the request (writes do nothing, reads return -1). This matches the
behavior of the other cfg mechanisms.
- Port the memory mapped configuration space access to amd64. On amd64
we simply use the direct map (via pmap_mapdev()) for the memory mapped
window.
- During acpi_attach() just after loading the ACPI tables, check for a
MCFG table. If it exists, call pciereg_cfgopen() on each subtable
(memory mapped window). For now we only support windows for domain 0
that start with bus 0. This removes the need for more chipset-specific
quirks in the MD code.
- Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets
since these machines should all have MCFG tables via ACPI.
- Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen()
earlier.

MFC after: 2 weeks

- Add support for memory mapped PCI config space access on Intel 915GM
and 5000P/V/Z chipsets.
- If the base address of the config space BAR is above 4GB for some reason
and this isn't a PAE kernel, then warn about this (under bootverbose)
and don't use the BAR.

PR: kern/126525
Submitted by: Arthur Hartwig @ Nokia
MFC after: 2 weeks

Use switch statements instead of if-else for enabling PCI-express config
space support.

MFC after: 1 week

Integrate support for xen in to i386 common code.

MFC after: 1 month

MFamd64: 1.109 of pci_cfgreg.c which changes pci_cfgdisable() into a nop
for type #1 similar to what other OS's do.

MFC after: 3 days

Adjust the code to probe for the PCI config mechanism to use.
- On amd64, just assume type #1 is always used. PCI 2.0 mandated
deprecated type #2 and required type #1 for all future bridges which
was well before amd64 existed.
- For i386, ignore whatever value was in 0xcf8 before testing for type #1
and instead rely on the other tests to determine if type #1 works. Some
newer machines leave garbage in 0xcf8 during boot and as a result the
kernel doesn't find PCI at all (which greatly confuses ACPI which expects
PCI to exist when PCI busses are in the namespace).

MFC after: 3 days
Discussed with: scottl

Replace a few magic numbers.

Add support for 7320 and 915 PCIe chipsets.

Submitted by: Gavin Atkinson <gavin.atkinson at ury dot york dot ac dot uk>
PR: kern/79139
Reviewed by: scottl

Provide a dummy NO_XBOX option that lives in opt_xbox.h for pc98.
This allows us to eliminate a three ifdef PC98 instances.

Fix pc98 build.

Add support for XBOX to the FreeBSD port. The xbox architecture is
nearly identical to wintel/ia32, with a couple of tweaks. Since it is
so similar to ia32, it is optionally added to a i386 kernel. This
port is preliminary, but seems to work well. Further improvements
will improve the interaction with syscons(4), port Linux nforce driver
and future versions of the xbox.

This supports the 64MB and 128MB boxes. You'll need the most recent
CVS version of Cromwell (the Linux BIOS for the XBOX) to boot.

Rink will be maintaining this port, and is interested in feedback.
He's setup a website http://xbox-bsd.nl to report the latest
developments.

Any silly mistakes are my fault.

Submitted by: Rink P.W. Springer rink at stack dot nl and
Ed Schouten ed at fxq dot nl

MFamd64: indent with tabs instead of spaces.

Undo the change to pci_cfgdisable() on i386 for now. It seems to fix
the amd64 case, but makes the i386 case fail even more often.

Modify the pci_cfgdisable() routine to bring it more in line with
other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0
to the config address register when using config mechanism 1 to turn
off config access. In fact, it can be downright troublesome, since it
seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause
it to sporadically botch reads from some devices. This is the cause
of the missing USP ports problem I was experiencing with my Sun Opteron
system.

Also correct the case for mechanism 2: it's only necessary to write
a 0 to the ENABLE port.

/* -> /*- for copyright notices, minor format tweaks as necessary

Remove a stray critical_exit().

Submitted by: johan

Expand the scope of the critical section in the PCIe read and write methods
on the advice of Alan Cox.

Due to a significant addition of code, add my copyright to this file. Also
note that the PCIe work was made possible due to hardware donations from
the FreeBSD Foundation and Intel. Thanks!

Add support for the memory-mapped PCI Express configuration mechanism. This
actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe
devices in the system, though only PCIe devices will respond to registers
higher than 256. This uses per-CPU pools of temporary mappings so that
the whole 256MB of configuration space doesn't have to be mapped all at
once. While the sf_buf API was considered for this, the fact that it
requires sleep locks and can return failure made it unsuitable for this use.

For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are
supported. Since there doesn't appear to be a compatible way to determine
northbridge support, new chipsets will have to be explicitely added in the
future.

Consistently use __inline instead of __inline__ as the former is an empty macro
in <sys/cdefs.h> for compilers without support for inline.

Trim a few things from the dmesg output and stick them under bootverbose to
cut down on the clutter including PCI interrupt routing, MTRR, pcibios,
etc.

Discussed with: USENIX Cabal

Switch to using the new $PIR interrupt routing code and remove the old
code. The pci_cfgreg.c file now just controls reading/writing PCI config
registers.

Replace an outb() during the test for configuration mechanism #1 with a
DELAY(1) instead. After wading through old commit logs, I found that the
outb() was added not as part of the test but as an intentional delay. In
fact, according to Shanley's PCI book, the configuration 1 data and address
ports should only be accessed using aligned 32-bit accesses (i.e. inl()
and outl()). Thus, using outb() to just the last byte of the port violates
the PCI spec it would seem. On at least one box doing so broke the probe
for PCI, whereas changing it to a DELAY(1) fixed the probe.

Reported by: Sean Welch <welchsm@earthlink.net>
MFC after: 1 week

New APIC support code:

- The apic interrupt entry points have been rewritten so that each entry
point can serve 32 different vectors. When the entry is executed, it
uses one of the 32-bit ISR registers to determine which vector in its
assigned range was triggered. Thus, the apic code can support 159
different interrupt vectors with only 5 entry points.
- We now always to disable the local APIC to work around an errata in
certain PPros and then re-enable it again if we decide to use the APICs
to route interrupts.
- We no longer map IO APICs or local APICs using special page table
entries. Instead, we just use pmap_mapdev(). We also no longer
export the virtual address of the local APIC as a global symbol to
the rest of the system, but only in local_apic.c. To aid this, the
APIC ID of each CPU is exported as a per-CPU variable.
- Interrupt sources are provided for each intpin on each IO APIC.
Currently, each source is given a unique interrupt vector meaning that
PCI interrupts are not shared on most machines with an I/O APIC.
That mapping for interrupt sources to interrupt vectors is up to the
APIC enumerator driver however.
- We no longer probe to see if we need to use mixed mode to route IRQ 0,
instead we always use mixed mode to route IRQ 0 for now. This can be
disabled via the 'NO_MIXED_MODE' kernel option.
- The npx(4) driver now always probes to see if a built-in FPU is present
since this test can now be performed with the new APIC code. However,
an SMP kernel will panic if there is more than one CPU and a built-in
FPU is not found.
- PCI interrupts are now properly routed when using APICs to route
interrupts, so remove the hack to psuedo-route interrupts when the
intpin register was read.
- The apic.h header was moved to apicreg.h and a new apicvar.h header
that declares the APIs used by the new APIC code was added.

Change all SYSCTLS which are readonly and have a related TUNABLE
from CTLFLAG_RD to CTLFLAG_RDTUN so that sysctl(8) can provide
more useful error messages.

We represent PCI intpin's two different ways. One is the way that the
intpin register is expressed in hardware where 0 means none, 1 means INTA,
2 INTB, etc. The other way is commonly used in loops where 0 means INTA,
1 means INTB, etc. The matchpin argument to pci_cfgintr_search() is
supposed to be the first form, but we passsed in a loop index of the
second. This fix adds one to the loop index to convert to the first form.

Reported by: Pavlin Radoslavov <pavlin@icir.org>

PC98 uses different mask of IRQ.

Add hw.pci.irq_override_mask, which is a mask of interrupts that are
considered to be good to try when it otherwise has no clue about which
interrupts to try. This is a band-aide and we really should try to
balance the IRQs that we arbitrarily pick, but it should help some
people that would otherwise get bad IRQs.

Use __FBSDID().

Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been
#if'ed out for a while. Complete the deed and tidy up some other bits.

We need to be able to call this stuff from outer edges of interrupt
handlers for devices that have the ISR bits in pci config space. Making
the bios code mpsafe was just too hairy. We had also stubbed it out some
time ago due to there simply being too much brokenness in too many systems.
This adds a leaf lock so that it is safe to use pci_read_config() and
pci_write_config() from interrupt handlers. We still will use pcibios
to do interrupt routing if there is no acpi.. [yes, I tested this]

Briefly glanced at by: imp

MFp4:
o Fix small style nit. This was supposed to be part of the last batch of
style fixes, but somehow didn't get merged.

MFp4:
o It turns out that we always need to try to route the interrupts for
the case where the $PIR tells us there can be only one. Some machines
require this, while others fail when we try to do this (bogusly, imho).
Since we have no apriori way of knowing which is which, we always try to
do the routing and hope for the best if things fail.
o Add some additional comments that state the obvious, but amplify it in
non-obvious ways (judging from the questions I've gotten).

This should un-break older laptops that still have to use PCIBIOS to route
interrupts.

Tested by: sam

Use 0xffffffff instead of -1 for id to compare against.
Use exact width types, since this is a MD file and won't be used elsewhere.
Fix a couple of resulting printf breakages

Bug found by: phk using Flexlint

o go ahead and route the interupt, even if it is supposedly unique.
there are some strange machines that seem to need this.
o delete bogus comment.
o don't use the the bios for read/writing config space. They interact badly
with SMP and being called from ISR. This brings -current in line with
-stable.

# make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we
# need to go back in a hurry.

Don't call function in return() for a void function.

Put verbose printf's in the PCI BIOS interrupt routing code under
if (bootverbose).

Axe unused include.

Make sure a $PIR table header has a valid length before accepting the table
as valid.

Submitted by: Michal Mertl <mime@traveller.cz>

Add a function pci_probe_route_table() that returns true if our PCI BIOS
supports interrupt routing and if the specified PCI bus is present in the
routing table.

Dump the $PIR table if booting verbose.

- Add a pci_cfgintr_valid() function to see if a given IRQ is a valid
IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table.
- Change pci_cfgintr() to except the current IRQ of a device as a fourth
argument and to use that IRQ for the device if it is valid.
- If an intpin entry in a $PIR entry has a link of 0, it means that that
intpin isn't connected to anything that can trigger an interrupt. Thus,
test the link against 0 to find invalid entries in the table instead of
implicitly relying on the irqs field to be zero. In the machines I have
looked at, intpin entries with a link of 0 often have the bits for all
possible interrupts for PCI devices set.

Add support for printing out the contents of a PCI BIOS $PIR interrupt
routing table on the console. Eventually it will be printed during
verbose boots.

Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,
not the 'entry' member. The entry point is formed from both a base and
a relative entry point. 'entry' is that relative offset. It is perfectly
valid to have an entry point with a relative offset of 0. PCIbios.ventry
is the virtual address of the entry point that takes both 'base' and
'entry' into account, thus it is the proper variable to test to see if we
have an entry point or not.

style(9)ize the whole file

Approved in concept a long time ago by: msmith

Use a common function to map the bogus intlines.
Don't require pin be non-zero before we map bogus intlines, always do it.
This fixes a number of problems on HP Omnibook computers.

Tested/Reviewed by: Brooks Davis

Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just having
it in pci_cfgregread() wasn't sufficent on at least the HP Omnibook 500.

Reviewed by: imp

o Work around bugs in the powerof2 macro: It thinks that 0 is a power of
2, but that's not the case. This fixes the case where there were slots
in the PIR table that had no bits set, but we assumed they did and used
strange results as a result.
o Map invalid INTLINE registers to 255 in pci_cfgreg.c. This should allow
us to remove the bogus checks in MI code for non-255 values.

I put these changes out for review a while ago, but no one responded
to them, so into current they go.

This should help us work better on machines that don't route
interrupts in the traditional way.

MFC After: 4286 millifortnights

Don't call the bios if the interrupt appaers to be already routed. Some
older PCI BIOSes hate this and this leads to panics when it is done. Also,
assume that a uniquely routed interrupt is already routed. This also
seems to help some older laptops with feable BIOSes cope.

The Libretto L series has no $PIR table, but does have a _PIR table.
This typo keeps us from properly routing an interrupt for CardBus
bridges on this machine. So, now we look for $PIR and then _PIR to
cope. With these changes, the Libretto L1 now works properly.
Evidentally, the idea comes from patch that the Japanese version of
RedHat (or against a Japanese version of Red Hat), but my Japanese
isn't good enough to to know for sure.

Reported by: Hiroyuki Aizu-san <eyes@navi.org>

# This may be an MFC candidate, but I'm not yet sure.

MFS: I was confused. This code wasn't in -current after all.

Merge in the irq 0 detection. Add comment about why.

If we have irq 0, ignore it like we do irq 255. Some BIOS writers aren't
careful like they should be.

It turns out that while Toshiba laptops don't want to route interrupts
multiple times, others do. The last strategy, which was to assume
that already routed interrupts were good and just return them doesn't
work for some laptops. So, instead, we have a new strategy: we notice
that we have an interrupt that's already routed. We go ahead and try
to route it, none the less. We will assume that it is correctly
routed, even if the route fails. We still assume that other failures
in the bios32 call are because the interrupt is NOT routed.

Note: some laptops do not support the bios32 interface to PCI BIOS and
we need to call it via the INT 2A interface. That is another windmill
to till at later.

Also correct a minor typo and minor whitespace nits.

Strong MFC candidate.

MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.
Check return value from bios32.

[[ Yes, I was bad and committed this to stable first. I should have done
the commit in the other order. ]]

The general conesnsus on irc was that pci bios for config registers
and such was just a bad idea and one that users should be forced to
enable if they want it. This patch introduces a hw.pci.enable_pcibios
tunable for those people. This does not impact the pcibios interrupt
routing at all.

Approved by: peter, msmith

Detect a certain type of PCIBIOS brain damage. For some reason,
some bios vendors took it apon themselves to "censor" the
host->pci bridges from PCIBIOS callers, even when the caller
explicitly asks for them. This includes certain Compaq machines
(eg: DL360) and some laptops.

If we detect this, shut down pcibios and revert to using IO
port bashing.

Under -current, apcica does a better job anyway.

Un-swap irq/link byte values so that printf works.

Free the memory we get from devclass_get_devices and device_get_children.

Submitted by: wpaul

Fix a warning due to missing prototype.

Remove declaration of airq variable from outer block. There were two
declarations of a variable of the same name. The one in the outer block
was unused and probably just slipped in at one point or another. This
silences a compiler warning.

Next phase in the PCI subsystem cleanup.

- Move PCI core code to dev/pci.
- Split bridge code out into separate modules.
- Remove the descriptive strings from the bridge drivers. If you
want to know what a device is, use pciconf. Add support for
broadly identifying devices based on class/subclass, and for
parsing a preloaded device identification database so that if
you want to waste the memory, you can identify *anything* we know
about.
- Remove machine-dependant code from the core PCI code. APIC interrupt
mapping is performed by shadowing the intline register in machine-
dependant code.
- Bring interrupt routing support to the Alpha
(although many platforms don't yet support routing or mapping
interrupts entirely correctly). This resulted in spamming
<sys/bus.h> into more places than it really should have gone.
- Put sys/dev on the kernel/modules include path. This avoids
having to change *all* the pci*.h includes.

Improve the PCI interrupt routing code. Now the process is as follows:

- Look for a hardwired interrupt in the routing table for this
bus/device/pin (we already did this).
- Look for another device with the same link byte which has a hardwired
interrupt.
- Look for a PCI device matching an entry with the same link byte
which has already been assigned an interrupt, and use that.
- Look for a routable interrupt listed in the "PCI only" interrupts
field and use that.
- Pick the first interrupt that's marked as routable and use that.

Call the BIOS to route the selected interrupt. Correctly calculate the
interrupt from the PCI routing table (ffs returns 1 for the rightmost
bit, not 0).

Remove debug writes introduced in prior commit

Add the ability to use the $PIR table in the BIOS to route interrupts
on demand.

Submitted by: msmith

Move the i386 PCI attachment code out of i386/isa back into i386/pci.

Split out the configuration space access primitives, as these are needed
elsewhere as well.

Get out the roto-rooter and clean up the abuse of nexus ivars by the
i386/isa/pcibus.c. This gets -current running again on multiple host->pci
machines after the most recent nexus commits. I had discussed this with
Mike Smith, but ended up doing it slightly differently to what we
discussed as it turned out cleaner this way. Mike was suggesting creating
a new resource (SYS_RES_PCIBUS) or something and using *_[gs]et_resource(),
but IMHO that wasn't ideal as SYS_RES_* is meant to be a global platform
property, not a quirk of a given implementation. This does use the ivar
methods but does so properly. It also now prints the physical pci bus that
a host->pci bridge (pcib) corresponds to.

Catch a few more bogosities in certain chipsets before they mess us up.
Some have dual host->PCI bridges for the same logical pci bus (!), eg:
some of the RCC chipsets. This is a 32/64 bit 33/66MHz and dual pci
voltage motherboard so persumably there are electical or signalling
differences but they are otherwise the same logical bus.
The new PCI probe code however was getting somewhat upset about it and
ended up creating two pci bridges to the same logical bus, which caused
devices on that logical bus to appear and be probed twice.

The ACPI data on this box correctly identifies this stuff, so bring on
ACPI! :-)

Take a shot at fixing multiple pci busses on i386.
pcib_set_bus() cannot be used on the new child because it is
meant to be used on the *pci* device (it looks at the parent internally)
not the pcib being added. Bite the bullet and use ivars for the bus
number to avoid any doubts about whether the softc is consistant between
probe and attach. This should not break the Alpha code.

* Completely rewrite the alpha busspace to hide the implementation from
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
which call busspace.
* Rework pci config accesses to route through the pcib device instead of
calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.

Add PnP probe methods to some common AT hardware drivers. In each case,
the PnP probe is merely a stub as we make assumptions about some of this
hardware before we have probed it.

Since these devices (with the exception of the speaker) are 'standard',
suppress output in the !bootverbose case to clean up the probe messages
somewhat.

Add OPTi 82C700 chipset.

Submitted by: sanpei@sanpei.org
PR: kern/18155 (part of)

Add 440MX chipset.

Submitted by: YOSHIMURA Hideaki <hideakiy@cs-tokyo01.chuosystem.co.jp>
References: [bsd-nomads:13764]

Don't assume that the PCI BIOS is going to clear the unused bits in %ecx
when it returns.

Some more i386-only BIOS-friendliness:

- Add support for using the PCI BIOS functions for configuration space
accesses, and make this the default.

- Make PNPBIOS the default (obsoletes the PNPBIOS config option).

- Add two new boot-time tunables to disable each of the above.

Add a workaround to allow us to detect the second pci bus on an HP
Netserver LS/2.

Approved by: jkh

Fix an uninitialised variable which affected probing on some machines.

Approved by: jkh
Reviewed by: gallatin

Allow allows peer pci buses which are directly connected to the RCC host pci
chipset to be probed & attached on newer Dell PowerEdge servers, such as
the 2400 and 4400.

Reviewed by: dfr, msmith, jlemon
Tested by: hnokubi@yyy.or.jp (in a previous incantation)
Approved by: jkh

Add PCI Id's for i810 chipsets.

PR: 16517
Submitted by: SAKIYAMA Nobuo <sakichan@lares.dti.ne.jp>
Approved by: jhk

Clean up the cfgmech/pci_mechanism debris. The reason for the existance
of this is no longer an issue as we have a replacement driver for the
one that needed it.

Reviewed by: dfr

Don't use a bogus bus number for Ross host-pci bridges.

PR: kern/15278
Submitted by: Ahmed Benani <ahmed_benani@urbanet.ch>

Remove the 'ivars' arguement to device_add_child() and
device_add_child_ordered(). 'ivars' may now be set using the
device_set_ivars() function.

This makes it easier for us to change how arbitrary data structures are
associated with a device_t. Eventually we won't be modifying device_t
to add additional pointers for ivars, softc data etc.

Despite my best efforts I've probably forgotten something so let me know
if this breaks anything. I've been running with this change for months
and its been quite involved actually isolating all the changes from
the rest of the local changes in my tree.

Reviewed by: peter, dfr

If we have found pci devices via pci_cfgopen(), but don't find a
host->pci bridge specifically, then add a pcib0 device on the motherboard
for the pci bus to hang off.

Requested by: Anders Andersson <anders@sanyusan.se>
Obtained from: dfr

Add text for the AMD-751 host-to-PCI and PCI-to-PCI (AGP) bridges.

$Id$ -> $FreeBSD$

Make the identify routine add itself with priority 100 to make sure it
goes after the npx/apm devices and any other motherboard devices that
may get added down the track.

Hopefully fix the previous commit, it caused *all* bridges to be detected
as PCI->HOST bridges on my (440BX) box.

My change is to remove the test at the beginning entirely, letting the
switch on the device ID happen first. If the device ID is unknown, then
(in the default case) check for the generic PCIS_BRIDGE_HOST tag. This
should allow wierd cases (eg: wpaul's IMS VL bridge) to work by using the
id override. This strategy is more in line with the other PCI match
methods we use elsewhere,

I only have a limited testbed, but having my USB etc devices detected as
PCI->HOST bridges doesn't look good.

Fix nexus_pcib_is_host_bridge() so that it detects my 486's PCI bus
correctly. It has the following code:

if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_HOST)
return NULL;

My 486 has an Integrated Micro Solutions PCI bridge which identifies
itself as subclass PCIS_BRIDGE_OTHER, not PCIS_BRIDGE_HOST. Consequently,
it gets ignored. In my opinion, the correct test should be:

if ((class != PCIC_BRIDGE) && (subclass != PCIS_BRIDGE_HOST))
return NULL;

That way the test still succeeds because the chip's class is PCIC_BRIDGE.
Clearly it's not reasonable to expect all host to PCI bridges to always
have a subclass of PCIS_BRIDGE_HOST since I've got one that doesn't.
This way the sanity test should remain relatively sane while still allowing
some oddball yet correct hardware to work. If somebody has a better way
to do it, go ahead and tweak the test, but be aware that
class == PCIC_BRIDGE and subclass == PCIS_BRIDGE_OTHER is a valid case.

While I was here, I also added an explicit ID string for the IMS chipset.
I also dealt with a minor style nit: it's bad karma not to have a default
case for your switch statements, but the one in this routine doesn't have
one. The default string of "Host to PCI bridge" is now assigned in a
default case of the switch statement instead of initializing "s" with the
string before the switch and then not having any default case.

Don't probe if pci_cfgopen() fails to find pci hardware, like we used to
to. This might have caused interesting things on non-PCI hardware if
PCI was compiled in.

Add support for multiple PCI busses directly connected to the nexus.
This is only partially complete, but allows 450NX-based systems with
more than one PCI bus to be used again.

Submitted by: dfr

Move pcibus (host -> pci bus) probe/attach routines from nexus
to pcibus.c. pci_cfgopen() becomes static and there are no more
bus #ifdef's in nexus.c.

Make the class code checks in function pci_cfgcheck less strict.
It failed to recognize the PCI bus in a system that had only an
old chip-set (class code 000000) and a Cyclom multiport serial
card on PCI bus 0, but no VGA card or disk or network controller.

PR: i386/5300
Submitted by: Nickolay N. Dudorov <nnd@itfs.nsk.su>

Removed unused #includes.

Yet another fix for configuration mechanism 1 register accesses:
Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).

Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15.

Set enable bit when writing the configuration address in configuration
mode 1. Omission of this bit makes all config register accesses fail in
on recent chip sets ...

(The problem was reported and debug output provided by: Steve Passe)

Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).

Mask out revision register in consistency test of class register.

Fix spelling of align and interrupt in comments.

Fix consistency test to not fail on pre PCI 2.0 motherboards

improve pcibus_check: Only assume PCI if at least one PCI to anything bridge
on bus 0.
This fixes problems with EISA-only systems mistakenly being assumed to support PCI.

Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.

Sync with <pci/pcibus.h>. pcibus.c unfortunately still compiled (with
only 3 or 4 warnings) when pb_maxirq went away.

Make the long-awaited change from $Id$ to $FreeBSD$

This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.

Make the code more consistant by using the INTR*MASK macros througout the
code.

Reviewed by: bde

[
Bruce suggest removing the macros completely, but I'm not up to that
task quite yet.
]

More merge and update.

(1) deleted #if 0

pc98/pc98/mse.c

(2) hold per-unit I/O ports in ed_softc

pc98/pc98/if_ed.c
pc98/pc98/if_ed98.h

(3) merge more files by segregating changes into headers.

new file (moved from pc98/pc98):

i386/isa/aic_98.h

deleted:

well, it's already in the commit message so I won't repeat the
long list here ;)

Submitted by: The FreeBSD(98) Development Team

Removed unused #includes of <i386/isa/icu.h> and <i386/isa/icu.h>. icu.h
is only used by the icu support modules and by a few drivers that know
too much about the icu (most only use it to convert `n' to `IRQn'). isa.h
is only used by ioconf.c and by a few drivers that know too much about
isa addresses (a few have to, because config is deficient).

Change CONF1_ENABLE_MSK to 0x7ff00000 in another attempt to decide
whether a system could possibly support PCI configuration mechanism 1
(or whether it rather is an EISA only system ...).

Make pcibus_check() ignore Device/Vendor IDs of all 0.

Removed now-unused #includes of <machine/cpu.h>. They were for bootverbose
being declared in the wrong place.

Count PCI irqs in up to 4 ISAish counters named `pci irqnn' instead of
in the clk0 counter.

Reviewed by: s

Completed function declarations and/or added prototypes and/or added
#includes to get prototypes.

pci now uses a different interrupt handler type for interrupts that it
dispatches and the isa interrupt handler type for the interrupts that
it handles.

Staticize and cleanup.

Make CONF1_ENABLE_MSK1 even less restriktive: Ignore slot ID ...

At least the ASUS Triton motherboards don't disable the PCI bus configuration
accesses after the BIOS bus scan. The previous revision made the assumption,
that every PCI motherboard did ...

Change the test on the initial value of the CONF1_ADDR_PORT register in a way
that makes the probe succeed on triton based motherboards, without breaking
the EISA motherboard that has some non-PCI register at the same address.

Go back to separate tests for configuration mechanism 1 and mechanism 2.
Require the state of the configuration enable bits to be OFF assuming
that the BIOS left them that way, as it should anyway to avoid bad things
to happen.

The tests themselves are copied from the previous release, with the
exception of CONF1_ENABLE_MSK1 having the LSB set. This bit should be
read back as '0', since only DWORD addresses are legal.

Fix bad typo: CONF1_ENABLE_RES1 was written CONF1_ENABLE_CHK1 ...

New approach to the PCI bus configuration mechanism probe problem:
- try to make sure there is any kind of PCI device
- if there is anything at port 0x0cf8, then check for mech. 1 or 2

Revert most changes of previous commit.
Changes relative to 1.12:
- Put extra instruction between outl()/inl() sequence to prevent the
old value being read back because of the bus capacitance.
- Additional check for existence of register at CONF2_ENABLE_PORT.

Another try to determine the PCI bus configuration mode (and whether
there is a PCI bus at all) ...

- Do not expect the chip sets to follow even very clearly expressed
requirements of the PCI 2.0 spec.
- Do not read back the value just written to an I/O port without making
sure that some other data have crossed the bus in between ...

Improved verification of configuration space accesses working:
Scan for devices instead of assuming that device 0 is present on bus 0
of every PCI motherboard.

Make the PCI host bridge probe code more robust when dealing with chip sets
that use configuration mode 1, but still violate the PCI 2.0 specs ...
(Required for the Compaq Proliant, for example.)

The PCI config mechanism 1 test failed for the Intel Aries.
Make it less strict ...

Submitted by: NIIMI Satoshi <sa2c@and.or.jp>

PCI configuration mechanism now determined by a method, that doesn't
fail on new hardware (Compaq Prolinea and Compaq Prosignea), and that
doesn't erroneously identify old mech. 2 chip sets as using mech. 1.
(See section 3.6.4.1.1 of the PCI bus specs rev. 2.0)

Correct pcibus_setup() to return as soon as one test succeeds.

Delete PCI PCI bridge simulator code ...

Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>

Remove spurious declaration of printf().

Submitted by: Michael Reifenberger <root@rz-wb.fh-sw.de>

New ISA specific PCI code.
Supports shared PCI interrupts.

Submitted by: Wolfgang Stanglmeier <wolf@kintaro.cologne.de>

Replace all remaining instances of `i386/include' by `machine' and fix
nearby #include inconsistencies.

Keep PCI_CONF_MODE in a safe place for later reference, if #defined.

Reviewed by: se
Submitted by: seb@erix.ericsson.se (Sebastian Strollo)

Initialisation of interrupt masks changed.

Reviewed by: se
Submitted by: wolf (Wolfgang Stanglmeier)

Reviewed by: se
Submitted by: wolf (Wolfgang Stanglmeier)
New ISA dependend file for PCI bus support.
Replaces sys/i386/pci/pcibios.c.