- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

This isn't functionally identical. In some cases a hint to disable
unit 0 would in fact disable all units.

This reverts r241856

Approved by: cperciva (implicit)

Now that device disabling is generic, remove extraneous code from the
device drivers that used to provide this feature.

Reviewed by: des
Approved by: cperciva
MFC after: 1 week

Use atomic load & store for TSC frequency. It may be overkill for amd64 but
safer for i386 because it can be easily over 4 GHz now. More worse, it can
be easily changed by user with 'machdep.tsc_freq' tunable (directly) or
cpufreq(4) (indirectly). Note it is intentionally not used in performance
critical paths to avoid performance regression (but we should, in theory).
Alternatively, we may add "virtual TSC" with lower frequency if maximum
frequency overflows 32 bits (and ignore possible incoherency as we do now).

Set C1 "I/O then Halt" capability bit for Intel EIST. Some broken BIOSes
refuse to load external SSDTs if this bit is unset for _PDC. It seems Linux
and OpenSolaris did the same long ago.

MFC after: 1 week

Few whitespace cleanups and comments tunings.

Submitted by: arundel

Core i5, same as previously Core2Duo, found to not set P-state for single
core lower then set on other cores. Do not try to test P-states on attach
on SMP systems. It is hopeless now and will just pollute verbose logs.
If needed, check still can be forced via loader tunable.

Introduce the new kernel sub-tree x86 which should contain all the code
shared and generalized between our current amd64, i386 and pc98.

This is just an initial step that should lead to a more complete effort.
For the moment, a very simple porting of cpufreq modules, BIOS calls and
the whole MD specific ISA bus part is added to the sub-tree but ideally
a lot of code might be added and more shared support should grow.

Sponsored by: Sandvine Incorporated
Reviewed by: emaste, kib, jhb, imp
Discussed on: arch
MFC: 3 weeks

Previous solution appeared to be unsufficient. After additional testing
I have found that it is not only desktop CPUs problem. but mobile also.
Probably AP on laptops just started initially at lower frequency, hiding
the problem.

Disable frequency validation by default, for systems with more then one CPU,
until we can implement it properly. It looks like making more harm now then
benefits. Add 'hw.est.strict' loader tunable to control it.

Now my iXsystems Invincibook is able to run at 800MHz lowest frequency,
instead of 1200MHz before, when 800MHz was incorrectly reported invalid.

Retry only once, if BIOS is completely broken and gives zero freqs.

Desktop Core2Duo/Core2Quad CPUs are unable to control frequency of single
CPU core, only pair of them. As result, both cores are running on highest
one of requested frequencies, and that is reported by status register.
Such behavior confuses frequency validation logic, as it runs on only
one core, as SMP is not yet launched, making EIST completely unusable.

To workaround this, add check for validation result. If we haven't found
at least two usable frequencies, then probably we are looking bad and have
to trust data provided by BIOS as-is.

Import ACPICA 20090521.

Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support.

Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").

Reviewed by: jhb, peter (early amd64 version)

Add a proper detach method to the est(4) driver using cpufreq_unregister().

MFC after: 1 week

Disable the code to generate a simple table from the status MSR by default.
This can be enabled by setting the 'hw.est.msr_info' tunable to 1.

If we are unable to obtain a frequency list from either ACPI or the static
tables, then attempt to build a simple list containing just the high and
low frequencies based on the current CPU frequency calculated during boot
and the contents of the MSR.

MFC after: 1 month

Attach the cpufreq child devices with specific orders to enforce relative
priority of some of the drivers that manage the same state (e.g. ichss0
vs est0). Specifically, powernow, est, and p4tcc are added at order 10,
ichss at order 20, and smist at order 30. Previously, some laptops were
seeing both ichss0 and est0 attaching and stomping on each other.

XXX: This isn't quite ideal, but works with the existing hacks, I think
what we really want instead is a single "speedstep0" device for CPUs
that the ichss, est, and smist drivers probe (but with differing
priorities).

MFC after: 1 week

After probing the available frequency settings, restore the CPU to run at
whatever frequency it started at instead of always picking the highest
frequency. The first version of this driver attempted to do this, but it
set the speed to the first frequency in the list rather than the value it
had saved.

MFC after: 1 week
Discussed with: rpaulo, phk

Remove unused variable saved_id16.

Pointy hat to: me
Pointed out by: jhb
MFC after: 1 week

Increase time we wait for things to settle to 1 millisecond,
10 microseconds is too short.

Always set the cpu to the highest frequency so that we get through
boot and don't handicap cpus where powerd(8) is not used.

- Don't execute cpuid to fetch the features. We already have the features
present in cpu_feature2. Also, use CPUID2_EST rather than a magic
number.
- Don't free the ACPI settings list in detach if we are going to fail the
request. Otherwise an attempt to kldunload est would free the array
but the driver would keep trying to use it.

MFC after: 1 week

In est_acpi_info(), initialize count before passing its pointer to
CPUFREQ_DRV_SETTINGS(). The value of count on input is used to
prefent overflow of the settings buffer passed into CPUFREQ_DRV_SETTINGS().

This corrects the "est: CPU supports Enhanced Speedstep, but is not recognized."
error on my system.

MFC after: 1 week

Validate the id16 values gathered from ACPI (previously a TODO item).
Style changes by me and njl.

Approved by: njl (mentor)
Reviewed by: njl (mentor)
Submitted by: Takeharu KATO <takeharu1219 at ybb.ne.jp>
PR: 119350
MFC after: 1 week

Add support for the VIA C7-M processor family.

Remove an unnecessary check of the table's bus clock. CPUs that
support this feature export only the high/low settings via the MSR,
packed into 32 bits.

Hardware from: Centaur Technologies
MFC after: 1 week

Add frequency-voltage tables for Intel 778, 758, 773, 753, and 733J
processors.

Obtained from: Intel Datasheet 302189-008

Print cpu_vendor and the MSR value if we don't support this processor
even though we're not asking people to contact us.

Requested by: njl

Remove the instruction to "contact the maintainer" for unrecognized
CPUs. Intel refuses to give me the information I need, and getting
more emails about this doesn't help.

Properly terminate the table generated from ACPI info. The cpufreq
settings are length-counted while the EST table is null-terminated.
This fixes extra garbage states being reported with ACPI probing.

Add support for _PDC/_OSC by advertising that we support direct access to
the PERF_CTL/STS MSRs via the new acpi_get_features() method. This should
allow newer systems to use SpeedStep.

Add support for probing EST settings from ACPI. This should handle more
modern CPUs that have multiple VID#s that aren't detectable via public
methods. We use the control value from acpi_perf as the id16 for setting
a given frequency.

Make a pass through all drivers checking specs for desired behavior on
SMP systems. It appears all drivers except ichss should attach to each
CPU and that settings should be performed on each CPU. Add comments about
this. Also, add a guard for p4tcc's identify method being called more than
once.

Correct an off-by-one error in the number of settings est announces.
The extraneous "0" state was not fatal but useless.

Support disabling individual cpufreq drivers with hints, e.g.,
hint.ichss.0.disabled="1"

Add the Enhanced SpeedStep driver (EST). Currently, this driver only works
on the previous generation of Pentium-M processors (Banias). Support for
Dothan and later processors involves working with acpi_perf(4) to extract
information about supported states. This driver should work on MP systems
including HTT. It is experimental and may have a few bugs but has been
tested to not crash at least.

Thanks to Colin Percival for his initial work on this driver.