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259065 |
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07-Dec-2013 |
gjb |
- Copy stable/10 (r259064) to releng/10.0 as part of the 10.0-RELEASE cycle. - Update __FreeBSD_version [1] - Set branch name to -RC1
[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so start releng/10.0 at '100' so the branch is started with a value ending in zero.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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238045 |
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02-Jul-2012 |
marcel |
Support lbc interrupts: o Save and clear the LTESR register in the interrupt handler. o In lbc_read_reg(), return the saved LTESR register value if applicable (i.e. when the saved value is not invalid (read: ~0U)). o In lbc_write_reg(), clear the bits in the saved register when when it's written to and when the asved value is not invalid. o Also in lbc_write_reg(), the LTESR register is unlocked (in H/W) when bit 1 of LTEATR is cleared. We use this to invalidate our saved LTESR register value. Subsequent reads and write go to H/W directly.
While here: o In lbc_read_reg() & lbc_write_reg(), add some belts and suspenders to catch when register offsets are out of range. o In lbc_attach(), initialize completely and don't leave something left for lbc_banks_enable().
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235937 |
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24-May-2012 |
marcel |
A few improvements: 1. Define all registers. These definitions are needed to support the FCM driver for direct-connect NAND. 2. Repurpose lbc_read_reg() and lbc_write_reg() for use by localbus attached device drivers. Use bus_space functions directly in the lbc driver itself. 3. Be smarter about programming LAWs and mapping memory. The ranges defined in the FDT are per bank (= chip select) and since we can have up to 8 banks, we could easily use more than 8 LAWs or TLB enrties when per-bank memory ranges need multiple LAWs or TLBs due to alignment or size constraints. We now combine all memory ranges into the fewest possible set of contiguous regions and program the hardware for that. Thus, a cleverly written FDT with 8 devices may still only need 1 LAW or 1 TLB entry. Note that the memory ranges can be assigned randomly to the banks. We sort as we build to handle that. 4. Support the FCM when programming the OR register. This is mostly for documention purposes as we do not have a way to define the mode for a bank. 5. Remove Semihalf-ism: do not define DEBUG (only to undefine it again).
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209908 |
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11-Jul-2010 |
raj |
Convert Freescale PowerPC platforms to FDT convention.
The following systems are affected:
- MPC8555CDS - MPC8572DS
This overhaul covers the following major changes:
- All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values).
- This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI.
- Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data.
Note that world for these platforms has to be built WITH_FDT.
Reviewed by: imp Sponsored by: The FreeBSD Foundation
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195799 |
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21-Jul-2009 |
raj |
Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX.
It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized.
Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf
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186288 |
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18-Dec-2008 |
raj |
Extend and improve MPC85XX Local Bus management.
- Make LBC resources management self-contained: introduce explicit LBC resources definition (much like the OCP), provide dedicated rman for LB mem space.
- Full configuration of an LB chip select device: program LAW and BR/OR, map into KVA, handle all LB attributes (bus width, machine select, ecc, write protect etc).
- Factor out LAW manipulation routines into shared code, adjust OCP area accordingly.
- Other LBC fixes and clean-ups.
Obtained from: Semihalf
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184250 |
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25-Oct-2008 |
marcel |
Add a driver for the Local Bus Controller.
Obtained from: Juniper Networks, Inc.
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