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257522 |
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01-Nov-2013 |
brooks |
MFC r256911, r256936
MFP4: 223121 (PIC portion), 225861, 227822, 229692 (PIC only), 229693, 230523, 1123614
Implement a driver for Robert Norton's PIC as an FDT interrupt controller. Devices whose interrupt-parent property points to a beripic
device will have their interrupt allocation, activation, and setup operations routed through the IC rather than down the traditional bus hierarchy.
This driver largely abstracts the underlying CPU away allowing the PIC to be implemented on CPU's other than BERI. Due to insufficient abstractions a small amount of MIPS specific code is currently required in fdt_mips.c and to implement counters.
Sponsored by: DARPA/AFRL Approved by: re (gjb)
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245335 |
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12-Jan-2013 |
rwatson |
Merge Perforce changeset 219933 and portions of 219962 (omits changes to unmerged BERI DTS files) to head:
Use the OFW compatible string "mips,mips4k" rather than "mips4k,cp0" for interrupt control using MIPS4k CP0.
Suggested by: thompsa
Implement a MIPS FDT PIC decode routine to use when no PIC has been configured, which assumes a cascade back to the nexus bus (e.g., the on-board CP0 interrupt management parts on the MIPS). If the soc bus in a MIPS DTS file is declared as "mips4k,cp0"-compatible, then this will be enabled. This is sufficient to allow IRQs to be configured on BERI.
Sponsored by: DARPA, AFRL
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