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142570 |
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26-Feb-2005 |
cognet |
Instead of using sysarch() to store-retrieve the tp, add a magic address, ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache line will be allocated and locked for this address, so that it will never go to RAM. On CPUs that does not, a page is allocated for it (it will be a bit slower, and is wrong for SMP, but should be fine for UP). The tp is still stored in the mdthread struct, and at each context switch, ARM_TP_ADDRESS gets updated.
Suggested by: davidxu
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135669 |
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23-Sep-2004 |
cognet |
Import partial support for the IQ31244 eval board (i80321 CPU). IQ80321 might work out of the box too, but I have no hardware to test. It works well enough to go multiuser. Network works, SATA does not, as I have no drive to test. Thanks to Intel for sending such a board.
Obtained from: NetBSD
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