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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation |
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204309 |
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25-Feb-2010 |
attilio |
Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98.
This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow.
Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
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187597 |
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22-Jan-2009 |
jkim |
Include a missing header file.
Reported by: thompsa, "build universe"
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187594 |
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22-Jan-2009 |
jkim |
Replace couple of strcmp(cpu_vendor, "foo") with cpu_vendor_id for i386 and hide i386-specific code under #ifdef.
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182401 |
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28-Aug-2008 |
jhb |
Fail detach if cpufreq_unregister() fails.
MFC after: 1 week
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181691 |
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13-Aug-2008 |
jhb |
Attach the cpufreq child devices with specific orders to enforce relative priority of some of the drivers that manage the same state (e.g. ichss0 vs est0). Specifically, powernow, est, and p4tcc are added at order 10, ichss at order 20, and smist at order 30. Previously, some laptops were seeing both ichss0 and est0 attaching and stomping on each other.
XXX: This isn't quite ideal, but works with the existing hacks, I think what we really want instead is a single "speedstep0" device for CPUs that the ichss, est, and smist drivers probe (but with differing priorities).
MFC after: 1 week
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170874 |
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17-Jun-2007 |
njl |
Use bus_dma to get a page in the first 4 GB. Since the physical address of the magic string is passed in a 32-bit register, we can't use high memory in the PAE case. This also eliminates a use of vtophys().
Tested by: Jeff Shimbo <jts767 / gmail.com> MFC after: 1 week
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145287 |
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19-Apr-2005 |
njl |
Add a driver for SMI-based SpeedStep. The hardware supports two frequency settings and is an older version of the same design used for ICH SpeedStep. It is only known to be available on PIIX4 chipsets.
Many thanks to Bruno Ducrot for writing the driver and Jon Noack for testing.
Submitted by: Bruno Ducrot
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