MFC r264601,264646,265766,267918,267919,267920:

Merge if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded
CPU Ethernet Core.

The current version operates on a simple PIO based interface connected
to a NetFPGA-10G port.

To avoid confusion: this driver operates on a CPU running on the FPGA,
e.g. BERI/mips, and is not suited for the PCI host interface.

Adjust the register layout to allow for 64bit registers in the
future for nf10bmac(4). Also, add support for and enable RX interrupts.

Allow switching between 32bit and 64bit bus width data access at compile
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.

Adjust comments to indicate the 32 or 64bit register widths.

Relnotes: yes
Sponsored by: DARPA/AFRL

MFC r263632:

For BERI on NetFPGA assume HZ=100 by default.

Remove the uart support in favour of a "jtag-uart" interface imitation
providing a much simpler interface, directly exported to the host,
allowing the toolchain to be shared with BERI on Altera. [1]

Submitted by: Jong Hun HAN (jong.han cl.cam.ac.uk) [1]
Sponsored by: DARPA/AFRL

MFC r259267:

Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA.

At this point we only support one CPU, the PIC, and a UART console.

Sponsored by: DARPA, AFRL

MFC r264601,264646,265766,267918,267919,267920:

Merge if_nf10bmac(4), a driver to support an NetFPGA-10G Embedded
CPU Ethernet Core.

The current version operates on a simple PIO based interface connected
to a NetFPGA-10G port.

To avoid confusion: this driver operates on a CPU running on the FPGA,
e.g. BERI/mips, and is not suited for the PCI host interface.

Adjust the register layout to allow for 64bit registers in the
future for nf10bmac(4). Also, add support for and enable RX interrupts.

Allow switching between 32bit and 64bit bus width data access at compile
time by setting NF10BMAC_64BIT and using a REGWTYPE #define to set correct
variable and return value widths.

Adjust comments to indicate the 32 or 64bit register widths.

Relnotes: yes
Sponsored by: DARPA/AFRL

MFC r263632:

For BERI on NetFPGA assume HZ=100 by default.

Remove the uart support in favour of a "jtag-uart" interface imitation
providing a much simpler interface, directly exported to the host,
allowing the toolchain to be shared with BERI on Altera. [1]

Submitted by: Jong Hun HAN (jong.han cl.cam.ac.uk) [1]
Sponsored by: DARPA/AFRL

MFC r259267:

Add an FDT DTS and MDROOT kernel configuration for BERI on NetFPGA.

At this point we only support one CPU, the PIC, and a UART console.

Sponsored by: DARPA, AFRL