Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Initialise the watchdog and UART frequencies.

For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.

For the AR934x, there's a different PLL setting for these, so they have
to be broken out.

Add the reference clock for each supported chip.

Obtained from: Linux (openwrt)

Further ar71xx MII support improvements.

* Flesh out the PLL configuration fetch function, which will return the PLL
configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
+ fetch the PLL configuration
+ write the PLL configuration
+ update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from: Linux/Atheros/OpenWRT

MII related infrastructure changes.

* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
+ arge0 supports all four (two for non-Gige interfaces.)
+ arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
+ Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
that is on the AP96 board. Autonegotiate is working fine, but there
still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT

style(9) changes.

Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.

Style(9) changes.

Join chip depended methods for arge0 and arge1 into single call with unit.

Approved by: adrian (mentor)

Remove duplicate header includes

Add the IP2 DDR flush handlers.

These aren't yet used in the interrupt handler path but should be.

Implement AR724x USB initialisation code.

This (again) still requires an offset for the AR913x/AR724x before USB will
function.

Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>

Add the missing AR724x DDR flush routines for if_arge0.

Submitted by: Luiz Otavio O Souza

Add some initial AR724X chipset support.

This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.