MFC r340212:
Sometimes the complete split packet may be queued too early and the
transaction translator will return a NAK. Ignore this message and
retry the complete split instead.

Sponsored by: Mellanox Technologies

MFC r339388:
Fix for reception of large full speed isochronous frames via the transaction
translator, when using the DWC OTG USB controller driver. Make sure to re-try
getting the complete split packets until a DATA0 packet is received. Larger
isochronous frames may be split into multiple MDATA packets terminated
by a single DATA0 packet.

PR: 230434
Sponsored by: Mellanox Technologies

MFC r302336:
Fix interrupt loop when switching from USB device to USB host mode by
clearing all endpoint interrupt bits.

PR: 210736

MFC r302306:
Fix detection of USB device disconnects in USB host mode when the USB
device is connected directly to the USB port of the DWC OTG, in this
case a RPI-zero.

PR: 210695

MFC r293192:
Fix for directly connected FULL or LOW speed USB devices.

MFC r290542:
Avoid using the bounce buffer when the source or destination buffer is
32-bits aligned. Merge the two bounce buffers into a single one. Some
rough tests showed that the DWC OTG throughput on RPI2 increased by
10% after this patch.

MFC r290195:
Reduce the DWC OTG interrupt load by not reading all the host channel
status registers for every interrupt. Check a common host channel
status interrupt register first, then conditionally read the
individual host channel status registers.

MFC r283067, r286118, r285638, r285935, r286778, r286780 and r286802:
- Make the FIFO configuration a bit more flexible for the DWC OTG in
device side mode.
- Limit the number of times we loop inside the DWC OTG poll handler to
avoid starving other fast interrupts. Fix a comment while at it.
- Optimise the DWC OTG host mode driver's transmit path
- Optimise the DWC OTG host mode driver's receive path
- Minor code refactor to avoid duplicating code.
- Handle NYET high speed tokens and predict NAK'ing is up next.
- Fixes for HIGH speed ISOCHRONOUS traffic.

MFC r283922:
Fix for control endpoint handling in the DWC OTG driver. The data
stage processing is only allowed after the setup complete event has
been received. Else a race may occur and the OUT data can be corrupted.
While at it ensure resetting a FIFO has the required wait loop.

MFC r283103:
Fix for DWC OTG device side isochronous transfers. The even or odd
isochronous frame bit needs to be flipped.

MFC r281881:
Disable multi process interrupts, because the current code doesn't use
them. Else we can end up in an infinite interrupt loop in USB device
mode.

MFC r279210:
Add support for the DWC OTG v2 chipset found in the STM32F4 series of
processors. Make sure we pullup the data lines in device mode when we
power on the port.

MFC r267044, r267120, r267210 and r267211:
Multiple fixes for FULL and LOW speed USB transfers going through
the DWC OTG as split transactions. INTERRUPT transfers should have
a higher chance of success after this series of patches and the
chance of data loss should be reduced.

MFC r266833:
Add some more spinlocks to protect the state of the USB transfer
queue. Rename some functions to indicate locking requirements.

MFC r265358, r265427, r265777, r265783,
r265806, r265872, r266012 and r266394:

- Multiple DWC OTG host mode related fixes, improvements and optimisations.
- Add full support for ISOCHRONOUS transfers to the DWC OTG driver.
- Use the interrupt filter to handle basic USB FIFO interrupts.
- Fixed unbalanced unlock in case of "dwc_otg_init_fifo()" failure.
- Add common spinlock to the USB bus structure.

MFC r283067, r286118, r285638, r285935, r286778, r286780 and r286802:
- Make the FIFO configuration a bit more flexible for the DWC OTG in
device side mode.
- Limit the number of times we loop inside the DWC OTG poll handler to
avoid starving other fast interrupts. Fix a comment while at it.
- Optimise the DWC OTG host mode driver's transmit path
- Optimise the DWC OTG host mode driver's receive path
- Minor code refactor to avoid duplicating code.
- Handle NYET high speed tokens and predict NAK'ing is up next.
- Fixes for HIGH speed ISOCHRONOUS traffic.

MFC r283922:
Fix for control endpoint handling in the DWC OTG driver. The data
stage processing is only allowed after the setup complete event has
been received. Else a race may occur and the OUT data can be corrupted.
While at it ensure resetting a FIFO has the required wait loop.

MFC r283103:
Fix for DWC OTG device side isochronous transfers. The even or odd
isochronous frame bit needs to be flipped.

MFC r281881:
Disable multi process interrupts, because the current code doesn't use
them. Else we can end up in an infinite interrupt loop in USB device
mode.

MFC r279210:
Add support for the DWC OTG v2 chipset found in the STM32F4 series of
processors. Make sure we pullup the data lines in device mode when we
power on the port.

MFC r267044, r267120, r267210 and r267211:
Multiple fixes for FULL and LOW speed USB transfers going through
the DWC OTG as split transactions. INTERRUPT transfers should have
a higher chance of success after this series of patches and the
chance of data loss should be reduced.

MFC r266833:
Add some more spinlocks to protect the state of the USB transfer
queue. Rename some functions to indicate locking requirements.

MFC r265358, r265427, r265777, r265783,
r265806, r265872, r266012 and r266394:

- Multiple DWC OTG host mode related fixes, improvements and optimisations.
- Add full support for ISOCHRONOUS transfers to the DWC OTG driver.
- Use the interrupt filter to handle basic USB FIFO interrupts.
- Fixed unbalanced unlock in case of "dwc_otg_init_fifo()" failure.
- Add common spinlock to the USB bus structure.