MFC r278770, r279114, r279215, r279338, r279543:

Add logic for handling new-style ARM cpu ID info.

Correct a comment which was exactly backwards from reality.

There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.

Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).

Revert incorrect casting.

MFC r271394, r271398:

Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.

Unify interrupts bit definition and usage. While here remove PSR_C_bit.

MFC r271310:

Rename new to newval in inline asm code, to avoid clashes with C++ new.

MFC r269403, r269405, r269410, r269414:

Add 64-bit atomic ops for armv6, and also for armv4 only in kernel code.
Use the new ops in the cddl code (and avoid defining functions with the
same names locally).

MFC 257189:

Fix an itt instruction. We need to execute both the mov and b instructions
when building for Thumb.

MFC 265861, 265870:

Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

MFC r261137, r261393

Correct the alignment of sp through functions that use UNWINDSVCFRAME.

Update all arm code that manipulates the PSR registers to use modern syntax.

MFC r278770, r279114, r279215, r279338, r279543:

Add logic for handling new-style ARM cpu ID info.

Correct a comment which was exactly backwards from reality.

There is no reason to do i+dcache writeback and invalidate when changing
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.

Add casting to make atomic ops work for pointers. (Apparently nobody has
ever done atomic ops on pointers before now on arm).

Revert incorrect casting.

MFC r271394, r271398:

Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
from asm.h as they were already defined in armreg.h.

Unify interrupts bit definition and usage. While here remove PSR_C_bit.

MFC r271310:

Rename new to newval in inline asm code, to avoid clashes with C++ new.

MFC r269403, r269405, r269410, r269414:

Add 64-bit atomic ops for armv6, and also for armv4 only in kernel code.
Use the new ops in the cddl code (and avoid defining functions with the
same names locally).

MFC 257189:

Fix an itt instruction. We need to execute both the mov and b instructions
when building for Thumb.

MFC 265861, 265870:

Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

MFC r261137, r261393

Correct the alignment of sp through functions that use UNWINDSVCFRAME.

Update all arm code that manipulates the PSR registers to use modern syntax.