replacing umlaute and fixing address in headers Haldeneggsteig -> Universitaetsstrasse

Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>

Create "ProcessManager" and "Domain" capabilities.

The ProcessManager capability is created by the CPU driver at startup and given
to init, where it will be passed on to the monitor and then the process manager
subsequently.

The Domain capability is an ID-like cap retypeable from the ProcessManager cap
above. The process management server can hence use the ProcessManager cap to
create Domain caps and give them to spawnd instances, to facilitate identifying
domains locally and globally.

Signed-off-by: Razvan Damachi <razvan.damachi@gmail.com>

init, pci: IO_CAP doesn't exist on ARMv8. Do not try to access it.

The changes should be abstracted into platform dependent code.

Signed-off-by: Moritz Hoffmann <moritz.hoffmann@hpe.com>

T258, T264, T270: Implement two-level cspace layout using L1/L2 CNode objects.

distops functionality is NYI.

This commit also makes the root cnodes explicit for sys_map(), closes T270.

Notable changes:
* LRPC LMP endpoints are regular capabilities in L2 cnode, no longer in root
cnode.
* Capability operations take a capability address for the root cnode relative
to which capability addresses are to be resolved. The root cnode capability
address must be resolvable in the current domains cspace.

Closes T264.

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

init: unify identical ifdef sections

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

T24: remove remaining SCC code

Signed-off-by: Moritz Hoffmann <moritz.hoffmann@inf.ethz.ch>

Clean merge of HP's ARMv8 code

This adds support for an ARMv8 core running in the GEM5 simulator

Signed-off-by: David Cock <david.cock@inf.ethz.ch>

T121: Create "real" BSP KCB cap for x86.

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

coreboot on the Xeon Phi:
added creating of the realmode segment capability in Kernel
added corectrl to the domains to be spawned by monitor on the Xeon Phi
adapted coreboot to use the predefined capability in taskcn/coreboot
slot.
added switch cases for the K1OM architecture in corectrl.

Make kernel create IPI cap which is passed to monitor.

This replaces the create_cap invocation in the monitor that creates an IPI cap
when someone requests a copy of it.

Addition of a card-side Xeon Phi Manager

added entries to gitignore

Addition of a second supercn.

It turned out that running Barrelfish on machines with lots of RAM will
results in a error during booting that the supercn has no more space
left. As soon as supercn0 has no space left, the allocator will switch
to the second supercn1 to store the capabilities.

Also memserver will get both endpoints and switches automatically to the
next supercn while building up the memory allocator. The maximum size
bits are extended to 40.

The offsets are adapted to support 1024GB physical memory.

The implementation has been tested on qemu prior commit.

Added K1OM switches to init Fixed hardcoded address in entry.S

Passing IO Capability to the monitor.

IRQ handling with hardcoded IRQ id (ehci interrupt) in monitor.

Interrupt handling on usb_manager level i.e. the host controller interrupt handlers
are called.

--HG--
rename : include/usb/class/usb_hub_request.h => include/usb/class/usb_hub.h
rename : usr/drivers/usb/usb_manager/usb_hub.c => usr/drivers/usb/usb_manager/hub/usb_hub.c
rename : usr/drivers/usb/usb_manager/usb_hub.h => usr/drivers/usb/usb_manager/hub/usb_hub.h

Changed kernel to hand out the capability for the device range and code for initializing the host controller

--HG--
rename : usr/drivers/usb/usb_manager/usb.c => usr/drivers/usb/usb_manager/usb_manager.c

remove support for Beehive

see the mailing list discussion at the end of December 2011 for motivation

Merge from ASPLOS tree.

Initial version of public stable barrelfish repository.