History log of /barrelfish-master/lib/barrelfish/arch/arm/entry.S
Revision Date Author Comments
# 9bd8d1d5 03-Apr-2019 Reto Achermann <reto.achermann@inf.ethz.ch>

replacing umlaute and fixing address in headers Haldeneggsteig -> Universitaetsstrasse

Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>


# 67f910f6 24-Jun-2016 David Cock <david.cock@inf.ethz.ch>

ARMv7: Switched to ARMv7+ TLS registers.

This frees up r9 for both kernel and user code.

Signed-off-by: David Cock <david.cock@inf.ethz.ch>


# a99b6f3f 04-Sep-2013 Claudio Föllmi <foellmic@student.ethz.ch>

timer interrupts enabled

fixed interrupt handler writing to trap area for non-trap interrupts
enabled timer interrupts at reasonable intervals (reasonable for -O2 and no caches)
added system call for restoring a context (just for armv7-m, replacing a x86-specific interrupt),
because the ONLY way to restore an IT block is by exiting handler mode (there is literally no other mechanism)
(will only be called if userspace tries to restore a context that was saved by the kernel, and comes from interrupting an IT block or a ldm/stm instruction)

You may want to use -O2 from now on (because we use interrupts, and thrashing is possible)
The compiler we use will probably complain up to 3 times ("unable to find a register to spill in class 'GENERAL_REGS'")
just retry the faulting compile instruction with -O1, and then restart make


# e1634dc8 29-Aug-2013 Claudio Föllmi <foellmic@student.ethz.ch>

basic armv7-m support

added new hake architecture "armv7-m"
added armv7-m port of kernel and libbarrelfish
fixed small arm_molly issues with parsing paths containing '-'

the port does not actually handle interrupts yet, but scheduling, spawning, and starting processes works
this update does not yet contain the armv7-a code to start the m3 core


# 9299dcef 08-Jul-2011 Stefan Kästle <stefan.kaestle@inf.ethz.ch>

Initial version of public stable barrelfish repository.