replacing umlaute and fixing address in headers Haldeneggsteig -> Universitaetsstrasse

Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>

fpu: unifing the fpu's context switching
x86_64: fixing the stack's alignment

Signed-off-by: Adam Turowski <adam.turowski@inf.ethz.ch>

fpu: unifing the fpu's context switching
x86_64: fixing the stack's alignment

Signed-off-by: Adam Turowski <adam.turowski@inf.ethz.ch>

fpu context switching for x86_64: the patch by Andrei Poenaru, 2017.01.14 14:24
Dear all,
While working on context switching I found a bug regarding the FPU context switching on the LRPC path: no FPU switching is performed on that path.
When 2 domains (using the FPU) communicate via LRPC the data stored in the registers is not correctly preserved. I was able to derive a test starting from 'lrpc_bench'.
In order to fix the issue, I implemented in assembly, on the LRPC path, the same logic as in 'fpu_lazy_top' (function called during a context switch on the normal kernel path).

Signed-off-by: Adam Turowski <adam.turowski@inf.ethz.ch>

systime: complete remove of kernel_now from x86_64

Signed-off-by: Adam Turowski <adam.turowski@inf.ethz.ch>

T258, T264, T270: Implement two-level cspace layout using L1/L2 CNode objects.

distops functionality is NYI.

This commit also makes the root cnodes explicit for sys_map(), closes T270.

Notable changes:
* LRPC LMP endpoints are regular capabilities in L2 cnode, no longer in root
cnode.
* Capability operations take a capability address for the root cnode relative
to which capability addresses are to be resolved. The root cnode capability
address must be resolvable in the current domains cspace.

Closes T264.

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

x86_64: kernel: remove all tabs from entry.S and reindent with 4 spaces

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

T187: x86_64: squash capability size to 64 bytes

Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>

Cleanup of Xeon Phi Kernel:

Merged duplicated code from k1om architecture with the X86_64 architecture.
No-longer files in arch/k1om have been deleted.

Reverted and applied Simon's patch to solve the supercn problem.

added entries to gitignore

Addition of a second supercn.

It turned out that running Barrelfish on machines with lots of RAM will
results in a error during booting that the supercn has no more space
left. As soon as supercn0 has no space left, the allocator will switch
to the second supercn1 to store the capabilities.

Also memserver will get both endpoints and switches automatically to the
next supercn while building up the memory allocator. The maximum size
bits are extended to 40.

The offsets are adapted to support 1024GB physical memory.

The implementation has been tested on qemu prior commit.

kernel: enable mapping of up to 1TB of physical memory.

kernel (x86_64): fix ambiguous operand size with 'cmp' and constant.

http://clang.llvm.org/compatibility.html#inline-asm

Initial version of public stable barrelfish repository.