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9bd8d1d5 |
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03-Apr-2019 |
Reto Achermann <reto.achermann@inf.ethz.ch> |
replacing umlaute and fixing address in headers Haldeneggsteig -> Universitaetsstrasse Signed-off-by: Reto Achermann <reto.achermann@inf.ethz.ch>
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a35f636b |
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30-Aug-2016 |
David Cock <david.cock@inf.ethz.ch> |
ARMv7: Manual coreboot works on Pandaboard Module that fact the UMP isn't working properly with ARM caches. Signed-off-by: David Cock <david.cock@inf.ethz.ch>
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1d898d1a |
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25-Jul-2016 |
Simon Gerber <simon.gerber@inf.ethz.ch> |
T272: armv7: implement two-level cspace layout Closes T272. Signed-off-by: Simon Gerber <simon.gerber@inf.ethz.ch>
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27701384 |
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28-Jun-2016 |
David Cock <david.cock@inf.ethz.ch> |
ARM: Removed traces of ARMv7-M and ARMv5 code. Signed-off-by: David Cock <david.cock@inf.ethz.ch>
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98ebc703 |
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28-Aug-2015 |
David Cock <david.cock@inf.ethz.ch> |
armv7-m (heteropanda) builds. Signed-off-by: David Cock <david.cock@inf.ethz.ch>
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a99b6f3f |
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04-Sep-2013 |
Claudio Föllmi <foellmic@student.ethz.ch> |
timer interrupts enabled fixed interrupt handler writing to trap area for non-trap interrupts enabled timer interrupts at reasonable intervals (reasonable for -O2 and no caches) added system call for restoring a context (just for armv7-m, replacing a x86-specific interrupt), because the ONLY way to restore an IT block is by exiting handler mode (there is literally no other mechanism) (will only be called if userspace tries to restore a context that was saved by the kernel, and comes from interrupting an IT block or a ldm/stm instruction) You may want to use -O2 from now on (because we use interrupts, and thrashing is possible) The compiler we use will probably complain up to 3 times ("unable to find a register to spill in class 'GENERAL_REGS'") just retry the faulting compile instruction with -O1, and then restart make
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9299dcef |
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08-Jul-2011 |
Stefan Kästle <stefan.kaestle@inf.ethz.ch> |
Initial version of public stable barrelfish repository.
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