1/*-
2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1997-2000 Nicolas Souchu
3 * Copyright (c) 2001 Alcove - Nicolas Souchu
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
|
29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 184176 2008-10-22 19:39:16Z jhb $");
| 29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 185003 2008-11-16 17:42:02Z jhb $");
|
30
31#include "opt_ppc.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/interrupt.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
| 30
31#include "opt_ppc.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/kernel.h>
37#include <sys/interrupt.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/proc.h>
|
41
| 41
|
42#include <machine/bus.h>
43#include <machine/resource.h>
44#include <sys/rman.h>
45
46#ifdef __i386__
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <machine/vmparam.h>
50#endif
51
52#include <dev/ppbus/ppbconf.h>
53#include <dev/ppbus/ppb_msq.h>
54
55#include <dev/ppc/ppcvar.h>
56#include <dev/ppc/ppcreg.h>
57
58#include "ppbus_if.h"
59
60static void ppcintr(void *arg);
61
62#define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
63#define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
64
65#define LOG_PPC(function, ppc, string) \
66 if (bootverbose) printf("%s: %s\n", function, string)
67
68#if defined(__i386__) && defined(PC98)
69#define PC98_IEEE_1284_DISABLE 0x100
70#define PC98_IEEE_1284_PORT 0x140
71#endif
72
73#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
74
75devclass_t ppc_devclass;
76const char ppc_driver_name[] = "ppc";
77
78static char *ppc_models[] = {
79 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
80 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
81 "SMC FDC37C935", "PC87303", 0
82};
83
84/* list of available modes */
85static char *ppc_avms[] = {
86 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
87 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
88 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
89 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
90};
91
92/* list of current executing modes
93 * Note that few modes do not actually exist.
94 */
95static char *ppc_modes[] = {
96 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
97 "EPP", "EPP", "EPP", "ECP",
98 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
99 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
100};
101
102static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
103
104#ifdef __i386__
105/*
106 * BIOS printer list - used by BIOS probe.
107 */
108#define BIOS_PPC_PORTS 0x408
109#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
110#define BIOS_MAX_PPC 4
111#endif
112
113/*
114 * ppc_ecp_sync() XXX
115 */
116void
| 42#include <machine/bus.h>
43#include <machine/resource.h>
44#include <sys/rman.h>
45
46#ifdef __i386__
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <machine/vmparam.h>
50#endif
51
52#include <dev/ppbus/ppbconf.h>
53#include <dev/ppbus/ppb_msq.h>
54
55#include <dev/ppc/ppcvar.h>
56#include <dev/ppc/ppcreg.h>
57
58#include "ppbus_if.h"
59
60static void ppcintr(void *arg);
61
62#define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */
63#define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */
64
65#define LOG_PPC(function, ppc, string) \
66 if (bootverbose) printf("%s: %s\n", function, string)
67
68#if defined(__i386__) && defined(PC98)
69#define PC98_IEEE_1284_DISABLE 0x100
70#define PC98_IEEE_1284_PORT 0x140
71#endif
72
73#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
74
75devclass_t ppc_devclass;
76const char ppc_driver_name[] = "ppc";
77
78static char *ppc_models[] = {
79 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
80 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
81 "SMC FDC37C935", "PC87303", 0
82};
83
84/* list of available modes */
85static char *ppc_avms[] = {
86 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
87 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
88 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
89 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
90};
91
92/* list of current executing modes
93 * Note that few modes do not actually exist.
94 */
95static char *ppc_modes[] = {
96 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
97 "EPP", "EPP", "EPP", "ECP",
98 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
99 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
100};
101
102static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
103
104#ifdef __i386__
105/*
106 * BIOS printer list - used by BIOS probe.
107 */
108#define BIOS_PPC_PORTS 0x408
109#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
110#define BIOS_MAX_PPC 4
111#endif
112
113/*
114 * ppc_ecp_sync() XXX
115 */
116void
|
117ppc_ecp_sync(device_t dev) {
118
| 117ppc_ecp_sync(device_t dev)
118{
|
119 int i, r;
120 struct ppc_data *ppc = DEVTOSOFTC(dev);
121
122 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
123 return;
124
125 r = r_ecr(ppc);
126 if ((r & 0xe0) != PPC_ECR_EPP)
127 return;
128
129 for (i = 0; i < 100; i++) {
130 r = r_ecr(ppc);
131 if (r & 0x1)
132 return;
133 DELAY(100);
134 }
135
136 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
137
138 return;
139}
140
141/*
142 * ppc_detect_fifo()
143 *
144 * Detect parallel port FIFO
145 */
146static int
147ppc_detect_fifo(struct ppc_data *ppc)
148{
149 char ecr_sav;
150 char ctr_sav, ctr, cc;
151 short i;
| 119 int i, r;
120 struct ppc_data *ppc = DEVTOSOFTC(dev);
121
122 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
123 return;
124
125 r = r_ecr(ppc);
126 if ((r & 0xe0) != PPC_ECR_EPP)
127 return;
128
129 for (i = 0; i < 100; i++) {
130 r = r_ecr(ppc);
131 if (r & 0x1)
132 return;
133 DELAY(100);
134 }
135
136 device_printf(dev, "ECP sync failed as data still present in FIFO.\n");
137
138 return;
139}
140
141/*
142 * ppc_detect_fifo()
143 *
144 * Detect parallel port FIFO
145 */
146static int
147ppc_detect_fifo(struct ppc_data *ppc)
148{
149 char ecr_sav;
150 char ctr_sav, ctr, cc;
151 short i;
|
152
| 152
|
153 /* save registers */
154 ecr_sav = r_ecr(ppc);
155 ctr_sav = r_ctr(ppc);
156
157 /* enter ECP configuration mode, no interrupt, no DMA */
158 w_ecr(ppc, 0xf4);
159
160 /* read PWord size - transfers in FIFO mode must be PWord aligned */
161 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
162
163 /* XXX 16 and 32 bits implementations not supported */
164 if (ppc->ppc_pword != PPC_PWORD_8) {
165 LOG_PPC(__func__, ppc, "PWord not supported");
166 goto error;
167 }
168
169 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
170 ctr = r_ctr(ppc);
171 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
172
173 /* enter ECP test mode, no interrupt, no DMA */
174 w_ecr(ppc, 0xd4);
175
176 /* flush the FIFO */
177 for (i=0; i<1024; i++) {
178 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
179 break;
180 cc = r_fifo(ppc);
181 }
182
183 if (i >= 1024) {
184 LOG_PPC(__func__, ppc, "can't flush FIFO");
185 goto error;
186 }
187
188 /* enable interrupts, no DMA */
189 w_ecr(ppc, 0xd0);
190
191 /* determine readIntrThreshold
192 * fill the FIFO until serviceIntr is set
193 */
194 for (i=0; i<1024; i++) {
195 w_fifo(ppc, (char)i);
196 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
197 /* readThreshold reached */
198 ppc->ppc_rthr = i+1;
199 }
200 if (r_ecr(ppc) & PPC_FIFO_FULL) {
201 ppc->ppc_fifo = i+1;
202 break;
203 }
204 }
205
206 if (i >= 1024) {
207 LOG_PPC(__func__, ppc, "can't fill FIFO");
208 goto error;
209 }
210
211 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
212 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
213 w_ecr(ppc, 0xd0); /* enable interrupts */
214
215 /* determine writeIntrThreshold
216 * empty the FIFO until serviceIntr is set
217 */
218 for (i=ppc->ppc_fifo; i>0; i--) {
219 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
220 LOG_PPC(__func__, ppc, "invalid data in FIFO");
221 goto error;
222 }
223 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
224 /* writeIntrThreshold reached */
225 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
226 }
227 /* if FIFO empty before the last byte, error */
228 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
229 LOG_PPC(__func__, ppc, "data lost in FIFO");
230 goto error;
231 }
232 }
233
234 /* FIFO must be empty after the last byte */
235 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
236 LOG_PPC(__func__, ppc, "can't empty the FIFO");
237 goto error;
238 }
| 153 /* save registers */
154 ecr_sav = r_ecr(ppc);
155 ctr_sav = r_ctr(ppc);
156
157 /* enter ECP configuration mode, no interrupt, no DMA */
158 w_ecr(ppc, 0xf4);
159
160 /* read PWord size - transfers in FIFO mode must be PWord aligned */
161 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
162
163 /* XXX 16 and 32 bits implementations not supported */
164 if (ppc->ppc_pword != PPC_PWORD_8) {
165 LOG_PPC(__func__, ppc, "PWord not supported");
166 goto error;
167 }
168
169 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
170 ctr = r_ctr(ppc);
171 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
172
173 /* enter ECP test mode, no interrupt, no DMA */
174 w_ecr(ppc, 0xd4);
175
176 /* flush the FIFO */
177 for (i=0; i<1024; i++) {
178 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
179 break;
180 cc = r_fifo(ppc);
181 }
182
183 if (i >= 1024) {
184 LOG_PPC(__func__, ppc, "can't flush FIFO");
185 goto error;
186 }
187
188 /* enable interrupts, no DMA */
189 w_ecr(ppc, 0xd0);
190
191 /* determine readIntrThreshold
192 * fill the FIFO until serviceIntr is set
193 */
194 for (i=0; i<1024; i++) {
195 w_fifo(ppc, (char)i);
196 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
197 /* readThreshold reached */
198 ppc->ppc_rthr = i+1;
199 }
200 if (r_ecr(ppc) & PPC_FIFO_FULL) {
201 ppc->ppc_fifo = i+1;
202 break;
203 }
204 }
205
206 if (i >= 1024) {
207 LOG_PPC(__func__, ppc, "can't fill FIFO");
208 goto error;
209 }
210
211 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
212 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
213 w_ecr(ppc, 0xd0); /* enable interrupts */
214
215 /* determine writeIntrThreshold
216 * empty the FIFO until serviceIntr is set
217 */
218 for (i=ppc->ppc_fifo; i>0; i--) {
219 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
220 LOG_PPC(__func__, ppc, "invalid data in FIFO");
221 goto error;
222 }
223 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
224 /* writeIntrThreshold reached */
225 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
226 }
227 /* if FIFO empty before the last byte, error */
228 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
229 LOG_PPC(__func__, ppc, "data lost in FIFO");
230 goto error;
231 }
232 }
233
234 /* FIFO must be empty after the last byte */
235 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
236 LOG_PPC(__func__, ppc, "can't empty the FIFO");
237 goto error;
238 }
|
239
| 239
|
240 w_ctr(ppc, ctr_sav);
241 w_ecr(ppc, ecr_sav);
242
243 return (0);
244
245error:
246 w_ctr(ppc, ctr_sav);
247 w_ecr(ppc, ecr_sav);
248
249 return (EINVAL);
250}
251
252static int
253ppc_detect_port(struct ppc_data *ppc)
254{
255
256 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
257 w_dtr(ppc, 0xaa);
258 if (r_dtr(ppc) != 0xaa)
259 return (0);
260
261 return (1);
262}
263
264/*
265 * EPP timeout, according to the PC87332 manual
266 * Semantics of clearing EPP timeout bit.
267 * PC87332 - reading SPP_STR does it...
268 * SMC - write 1 to EPP timeout bit XXX
269 * Others - (?) write 0 to EPP timeout bit
270 */
271static void
272ppc_reset_epp_timeout(struct ppc_data *ppc)
273{
274 register char r;
275
276 r = r_str(ppc);
277 w_str(ppc, r | 0x1);
278 w_str(ppc, r & 0xfe);
279
280 return;
281}
282
283static int
284ppc_check_epp_timeout(struct ppc_data *ppc)
285{
286 ppc_reset_epp_timeout(ppc);
287
288 return (!(r_str(ppc) & TIMEOUT));
289}
290
291/*
292 * Configure current operating mode
293 */
294static int
295ppc_generic_setmode(struct ppc_data *ppc, int mode)
296{
297 u_char ecr = 0;
298
299 /* check if mode is available */
300 if (mode && !(ppc->ppc_avm & mode))
301 return (EINVAL);
302
303 /* if ECP mode, configure ecr register */
304 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
305 /* return to byte mode (keeping direction bit),
306 * no interrupt, no DMA to be able to change to
307 * ECP
308 */
309 w_ecr(ppc, PPC_ECR_RESET);
310 ecr = PPC_DISABLE_INTR;
311
312 if (mode & PPB_EPP)
313 return (EINVAL);
314 else if (mode & PPB_ECP)
315 /* select ECP mode */
316 ecr |= PPC_ECR_ECP;
317 else if (mode & PPB_PS2)
318 /* select PS2 mode with ECP */
319 ecr |= PPC_ECR_PS2;
320 else
321 /* select COMPATIBLE/NIBBLE mode */
322 ecr |= PPC_ECR_STD;
323
324 w_ecr(ppc, ecr);
325 }
326
327 ppc->ppc_mode = mode;
328
329 return (0);
330}
331
332/*
333 * The ppc driver is free to choose options like FIFO or DMA
334 * if ECP mode is available.
335 *
336 * The 'RAW' option allows the upper drivers to force the ppc mode
337 * even with FIFO, DMA available.
338 */
339static int
340ppc_smclike_setmode(struct ppc_data *ppc, int mode)
341{
342 u_char ecr = 0;
343
344 /* check if mode is available */
345 if (mode && !(ppc->ppc_avm & mode))
346 return (EINVAL);
347
348 /* if ECP mode, configure ecr register */
349 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
350 /* return to byte mode (keeping direction bit),
351 * no interrupt, no DMA to be able to change to
352 * ECP or EPP mode
353 */
354 w_ecr(ppc, PPC_ECR_RESET);
355 ecr = PPC_DISABLE_INTR;
356
357 if (mode & PPB_EPP)
358 /* select EPP mode */
359 ecr |= PPC_ECR_EPP;
360 else if (mode & PPB_ECP)
361 /* select ECP mode */
362 ecr |= PPC_ECR_ECP;
363 else if (mode & PPB_PS2)
364 /* select PS2 mode with ECP */
365 ecr |= PPC_ECR_PS2;
366 else
367 /* select COMPATIBLE/NIBBLE mode */
368 ecr |= PPC_ECR_STD;
369
370 w_ecr(ppc, ecr);
371 }
372
373 ppc->ppc_mode = mode;
374
375 return (0);
376}
377
378#ifdef PPC_PROBE_CHIPSET
379/*
380 * ppc_pc873xx_detect
381 *
382 * Probe for a Natsemi PC873xx-family part.
383 *
384 * References in this function are to the National Semiconductor
385 * PC87332 datasheet TL/C/11930, May 1995 revision.
386 */
387static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
388static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
389static int pc873xx_irqtab[] = {5, 7, 5, 0};
390
391static int pc873xx_regstab[] = {
392 PC873_FER, PC873_FAR, PC873_PTR,
393 PC873_FCR, PC873_PCR, PC873_PMC,
394 PC873_TUP, PC873_SID, PC873_PNP0,
395 PC873_PNP1, PC873_LPTBA, -1
396};
397
398static char *pc873xx_rnametab[] = {
399 "FER", "FAR", "PTR", "FCR", "PCR",
400 "PMC", "TUP", "SID", "PNP0", "PNP1",
401 "LPTBA", NULL
402};
403
404static int
405ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
406{
407 static int index = 0;
408 int idport, irq;
409 int ptr, pcr, val, i;
| 240 w_ctr(ppc, ctr_sav);
241 w_ecr(ppc, ecr_sav);
242
243 return (0);
244
245error:
246 w_ctr(ppc, ctr_sav);
247 w_ecr(ppc, ecr_sav);
248
249 return (EINVAL);
250}
251
252static int
253ppc_detect_port(struct ppc_data *ppc)
254{
255
256 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
257 w_dtr(ppc, 0xaa);
258 if (r_dtr(ppc) != 0xaa)
259 return (0);
260
261 return (1);
262}
263
264/*
265 * EPP timeout, according to the PC87332 manual
266 * Semantics of clearing EPP timeout bit.
267 * PC87332 - reading SPP_STR does it...
268 * SMC - write 1 to EPP timeout bit XXX
269 * Others - (?) write 0 to EPP timeout bit
270 */
271static void
272ppc_reset_epp_timeout(struct ppc_data *ppc)
273{
274 register char r;
275
276 r = r_str(ppc);
277 w_str(ppc, r | 0x1);
278 w_str(ppc, r & 0xfe);
279
280 return;
281}
282
283static int
284ppc_check_epp_timeout(struct ppc_data *ppc)
285{
286 ppc_reset_epp_timeout(ppc);
287
288 return (!(r_str(ppc) & TIMEOUT));
289}
290
291/*
292 * Configure current operating mode
293 */
294static int
295ppc_generic_setmode(struct ppc_data *ppc, int mode)
296{
297 u_char ecr = 0;
298
299 /* check if mode is available */
300 if (mode && !(ppc->ppc_avm & mode))
301 return (EINVAL);
302
303 /* if ECP mode, configure ecr register */
304 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
305 /* return to byte mode (keeping direction bit),
306 * no interrupt, no DMA to be able to change to
307 * ECP
308 */
309 w_ecr(ppc, PPC_ECR_RESET);
310 ecr = PPC_DISABLE_INTR;
311
312 if (mode & PPB_EPP)
313 return (EINVAL);
314 else if (mode & PPB_ECP)
315 /* select ECP mode */
316 ecr |= PPC_ECR_ECP;
317 else if (mode & PPB_PS2)
318 /* select PS2 mode with ECP */
319 ecr |= PPC_ECR_PS2;
320 else
321 /* select COMPATIBLE/NIBBLE mode */
322 ecr |= PPC_ECR_STD;
323
324 w_ecr(ppc, ecr);
325 }
326
327 ppc->ppc_mode = mode;
328
329 return (0);
330}
331
332/*
333 * The ppc driver is free to choose options like FIFO or DMA
334 * if ECP mode is available.
335 *
336 * The 'RAW' option allows the upper drivers to force the ppc mode
337 * even with FIFO, DMA available.
338 */
339static int
340ppc_smclike_setmode(struct ppc_data *ppc, int mode)
341{
342 u_char ecr = 0;
343
344 /* check if mode is available */
345 if (mode && !(ppc->ppc_avm & mode))
346 return (EINVAL);
347
348 /* if ECP mode, configure ecr register */
349 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
350 /* return to byte mode (keeping direction bit),
351 * no interrupt, no DMA to be able to change to
352 * ECP or EPP mode
353 */
354 w_ecr(ppc, PPC_ECR_RESET);
355 ecr = PPC_DISABLE_INTR;
356
357 if (mode & PPB_EPP)
358 /* select EPP mode */
359 ecr |= PPC_ECR_EPP;
360 else if (mode & PPB_ECP)
361 /* select ECP mode */
362 ecr |= PPC_ECR_ECP;
363 else if (mode & PPB_PS2)
364 /* select PS2 mode with ECP */
365 ecr |= PPC_ECR_PS2;
366 else
367 /* select COMPATIBLE/NIBBLE mode */
368 ecr |= PPC_ECR_STD;
369
370 w_ecr(ppc, ecr);
371 }
372
373 ppc->ppc_mode = mode;
374
375 return (0);
376}
377
378#ifdef PPC_PROBE_CHIPSET
379/*
380 * ppc_pc873xx_detect
381 *
382 * Probe for a Natsemi PC873xx-family part.
383 *
384 * References in this function are to the National Semiconductor
385 * PC87332 datasheet TL/C/11930, May 1995 revision.
386 */
387static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
388static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
389static int pc873xx_irqtab[] = {5, 7, 5, 0};
390
391static int pc873xx_regstab[] = {
392 PC873_FER, PC873_FAR, PC873_PTR,
393 PC873_FCR, PC873_PCR, PC873_PMC,
394 PC873_TUP, PC873_SID, PC873_PNP0,
395 PC873_PNP1, PC873_LPTBA, -1
396};
397
398static char *pc873xx_rnametab[] = {
399 "FER", "FAR", "PTR", "FCR", "PCR",
400 "PMC", "TUP", "SID", "PNP0", "PNP1",
401 "LPTBA", NULL
402};
403
404static int
405ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
406{
407 static int index = 0;
408 int idport, irq;
409 int ptr, pcr, val, i;
|
410
| 410
|
411 while ((idport = pc873xx_basetab[index++])) {
| 411 while ((idport = pc873xx_basetab[index++])) {
|
412
| 412
|
413 /* XXX should check first to see if this location is already claimed */
414
415 /*
416 * Pull the 873xx through the power-on ID cycle (2.2,1.).
417 * We can't use this to locate the chip as it may already have
418 * been used by the BIOS.
419 */
420 (void)inb(idport); (void)inb(idport);
421 (void)inb(idport); (void)inb(idport);
422
423 /*
424 * Read the SID byte. Possible values are :
425 *
426 * 01010xxx PC87334
427 * 0001xxxx PC87332
428 * 01110xxx PC87306
429 * 00110xxx PC87303
430 */
431 outb(idport, PC873_SID);
432 val = inb(idport + 1);
433 if ((val & 0xf0) == 0x10) {
434 ppc->ppc_model = NS_PC87332;
435 } else if ((val & 0xf8) == 0x70) {
436 ppc->ppc_model = NS_PC87306;
437 } else if ((val & 0xf8) == 0x50) {
438 ppc->ppc_model = NS_PC87334;
439 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
440 documentation, but probing
441 yielded 0x40... */
442 ppc->ppc_model = NS_PC87303;
443 } else {
444 if (bootverbose && (val != 0xff))
445 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
446 continue ; /* not recognised */
447 }
448
449 /* print registers */
450 if (bootverbose) {
451 printf("PC873xx");
452 for (i=0; pc873xx_regstab[i] != -1; i++) {
453 outb(idport, pc873xx_regstab[i]);
454 printf(" %s=0x%x", pc873xx_rnametab[i],
455 inb(idport + 1) & 0xff);
456 }
457 printf("\n");
458 }
| 413 /* XXX should check first to see if this location is already claimed */
414
415 /*
416 * Pull the 873xx through the power-on ID cycle (2.2,1.).
417 * We can't use this to locate the chip as it may already have
418 * been used by the BIOS.
419 */
420 (void)inb(idport); (void)inb(idport);
421 (void)inb(idport); (void)inb(idport);
422
423 /*
424 * Read the SID byte. Possible values are :
425 *
426 * 01010xxx PC87334
427 * 0001xxxx PC87332
428 * 01110xxx PC87306
429 * 00110xxx PC87303
430 */
431 outb(idport, PC873_SID);
432 val = inb(idport + 1);
433 if ((val & 0xf0) == 0x10) {
434 ppc->ppc_model = NS_PC87332;
435 } else if ((val & 0xf8) == 0x70) {
436 ppc->ppc_model = NS_PC87306;
437 } else if ((val & 0xf8) == 0x50) {
438 ppc->ppc_model = NS_PC87334;
439 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
440 documentation, but probing
441 yielded 0x40... */
442 ppc->ppc_model = NS_PC87303;
443 } else {
444 if (bootverbose && (val != 0xff))
445 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
446 continue ; /* not recognised */
447 }
448
449 /* print registers */
450 if (bootverbose) {
451 printf("PC873xx");
452 for (i=0; pc873xx_regstab[i] != -1; i++) {
453 outb(idport, pc873xx_regstab[i]);
454 printf(" %s=0x%x", pc873xx_rnametab[i],
455 inb(idport + 1) & 0xff);
456 }
457 printf("\n");
458 }
|
459
| 459
|
460 /*
461 * We think we have one. Is it enabled and where we want it to be?
462 */
463 outb(idport, PC873_FER);
464 val = inb(idport + 1);
465 if (!(val & PC873_PPENABLE)) {
466 if (bootverbose)
467 printf("PC873xx parallel port disabled\n");
468 continue;
469 }
470 outb(idport, PC873_FAR);
471 val = inb(idport + 1);
472 /* XXX we should create a driver instance for every port found */
473 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
474
475 /* First try to change the port address to that requested... */
476
477 switch(ppc->ppc_base) {
478 case 0x378:
479 val &= 0xfc;
480 break;
481
482 case 0x3bc:
483 val &= 0xfd;
484 break;
485
486 case 0x278:
487 val &= 0xfe;
488 break;
489
490 default:
491 val &= 0xfd;
492 break;
493 }
494
495 outb(idport, PC873_FAR);
496 outb(idport + 1, val);
497 outb(idport + 1, val);
498
499 /* Check for success by reading back the value we supposedly
500 wrote and comparing...*/
501
502 outb(idport, PC873_FAR);
503 val = inb(idport + 1) & 0x3;
504
505 /* If we fail, report the failure... */
506
507 if (pc873xx_porttab[val] != ppc->ppc_base) {
508 if (bootverbose)
509 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
510 pc873xx_porttab[val], ppc->ppc_base);
511 }
512 continue;
513 }
514
515 outb(idport, PC873_PTR);
| 460 /*
461 * We think we have one. Is it enabled and where we want it to be?
462 */
463 outb(idport, PC873_FER);
464 val = inb(idport + 1);
465 if (!(val & PC873_PPENABLE)) {
466 if (bootverbose)
467 printf("PC873xx parallel port disabled\n");
468 continue;
469 }
470 outb(idport, PC873_FAR);
471 val = inb(idport + 1);
472 /* XXX we should create a driver instance for every port found */
473 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
474
475 /* First try to change the port address to that requested... */
476
477 switch(ppc->ppc_base) {
478 case 0x378:
479 val &= 0xfc;
480 break;
481
482 case 0x3bc:
483 val &= 0xfd;
484 break;
485
486 case 0x278:
487 val &= 0xfe;
488 break;
489
490 default:
491 val &= 0xfd;
492 break;
493 }
494
495 outb(idport, PC873_FAR);
496 outb(idport + 1, val);
497 outb(idport + 1, val);
498
499 /* Check for success by reading back the value we supposedly
500 wrote and comparing...*/
501
502 outb(idport, PC873_FAR);
503 val = inb(idport + 1) & 0x3;
504
505 /* If we fail, report the failure... */
506
507 if (pc873xx_porttab[val] != ppc->ppc_base) {
508 if (bootverbose)
509 printf("PC873xx at 0x%x not for driver at port 0x%x\n",
510 pc873xx_porttab[val], ppc->ppc_base);
511 }
512 continue;
513 }
514
515 outb(idport, PC873_PTR);
|
516 ptr = inb(idport + 1);
| 516 ptr = inb(idport + 1);
|
517
518 /* get irq settings */
519 if (ppc->ppc_base == 0x378)
520 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
521 else
522 irq = pc873xx_irqtab[val];
523
524 if (bootverbose)
525 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
| 517
518 /* get irq settings */
519 if (ppc->ppc_base == 0x378)
520 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
521 else
522 irq = pc873xx_irqtab[val];
523
524 if (bootverbose)
525 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
|
526
| 526
|
527 /*
528 * Check if irq settings are correct
529 */
530 if (irq != ppc->ppc_irq) {
531 /*
532 * If the chipset is not locked and base address is 0x378,
533 * we have another chance
534 */
535 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
536 if (ppc->ppc_irq == 7) {
537 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
538 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
539 } else {
540 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
541 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
542 }
543 if (bootverbose)
544 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
545 } else {
546 if (bootverbose)
547 printf("PC873xx sorry, can't change irq setting\n");
548 }
549 } else {
550 if (bootverbose)
551 printf("PC873xx irq settings are correct\n");
552 }
553
554 outb(idport, PC873_PCR);
555 pcr = inb(idport + 1);
| 527 /*
528 * Check if irq settings are correct
529 */
530 if (irq != ppc->ppc_irq) {
531 /*
532 * If the chipset is not locked and base address is 0x378,
533 * we have another chance
534 */
535 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
536 if (ppc->ppc_irq == 7) {
537 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
538 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
539 } else {
540 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
541 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
542 }
543 if (bootverbose)
544 printf("PC873xx irq set to %d\n", ppc->ppc_irq);
545 } else {
546 if (bootverbose)
547 printf("PC873xx sorry, can't change irq setting\n");
548 }
549 } else {
550 if (bootverbose)
551 printf("PC873xx irq settings are correct\n");
552 }
553
554 outb(idport, PC873_PCR);
555 pcr = inb(idport + 1);
|
556
| 556
|
557 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
558 if (bootverbose)
559 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
560
561 ppc->ppc_avm |= PPB_NIBBLE;
562 if (bootverbose)
563 printf(", NIBBLE");
564
565 if (pcr & PC873_EPPEN) {
| 557 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
558 if (bootverbose)
559 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
560
561 ppc->ppc_avm |= PPB_NIBBLE;
562 if (bootverbose)
563 printf(", NIBBLE");
564
565 if (pcr & PC873_EPPEN) {
|
566 ppc->ppc_avm |= PPB_EPP;
| 566 ppc->ppc_avm |= PPB_EPP;
|
567
568 if (bootverbose)
569 printf(", EPP");
570
571 if (pcr & PC873_EPP19)
572 ppc->ppc_epp = EPP_1_9;
573 else
574 ppc->ppc_epp = EPP_1_7;
575
576 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
577 outb(idport, PC873_PTR);
578 ptr = inb(idport + 1);
579 if (ptr & PC873_EPPRDIR)
580 printf(", Regular mode");
581 else
582 printf(", Automatic mode");
583 }
584 } else if (pcr & PC873_ECPEN) {
585 ppc->ppc_avm |= PPB_ECP;
586 if (bootverbose)
587 printf(", ECP");
588
589 if (pcr & PC873_ECPCLK) { /* XXX */
590 ppc->ppc_avm |= PPB_PS2;
591 if (bootverbose)
592 printf(", PS/2");
593 }
594 } else {
595 outb(idport, PC873_PTR);
596 ptr = inb(idport + 1);
597 if (ptr & PC873_EXTENDED) {
598 ppc->ppc_avm |= PPB_SPP;
| 567
568 if (bootverbose)
569 printf(", EPP");
570
571 if (pcr & PC873_EPP19)
572 ppc->ppc_epp = EPP_1_9;
573 else
574 ppc->ppc_epp = EPP_1_7;
575
576 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
577 outb(idport, PC873_PTR);
578 ptr = inb(idport + 1);
579 if (ptr & PC873_EPPRDIR)
580 printf(", Regular mode");
581 else
582 printf(", Automatic mode");
583 }
584 } else if (pcr & PC873_ECPEN) {
585 ppc->ppc_avm |= PPB_ECP;
586 if (bootverbose)
587 printf(", ECP");
588
589 if (pcr & PC873_ECPCLK) { /* XXX */
590 ppc->ppc_avm |= PPB_PS2;
591 if (bootverbose)
592 printf(", PS/2");
593 }
594 } else {
595 outb(idport, PC873_PTR);
596 ptr = inb(idport + 1);
597 if (ptr & PC873_EXTENDED) {
598 ppc->ppc_avm |= PPB_SPP;
|
599 if (bootverbose)
600 printf(", SPP");
| 599 if (bootverbose)
600 printf(", SPP");
|
601 }
602 }
603 } else {
604 if (bootverbose)
605 printf("PC873xx unlocked");
606
607 if (chipset_mode & PPB_ECP) {
608 if ((chipset_mode & PPB_EPP) && bootverbose)
609 printf(", ECP+EPP not supported");
610
611 pcr &= ~PC873_EPPEN;
612 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
613 outb(idport + 1, pcr);
614 outb(idport + 1, pcr);
615
616 if (bootverbose)
617 printf(", ECP");
618
619 } else if (chipset_mode & PPB_EPP) {
620 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
621 pcr |= (PC873_EPPEN | PC873_EPP19);
622 outb(idport + 1, pcr);
623 outb(idport + 1, pcr);
624
625 ppc->ppc_epp = EPP_1_9; /* XXX */
626
627 if (bootverbose)
628 printf(", EPP1.9");
629
630 /* enable automatic direction turnover */
631 if (ppc->ppc_model == NS_PC87332) {
632 outb(idport, PC873_PTR);
633 ptr = inb(idport + 1);
634 ptr &= ~PC873_EPPRDIR;
635 outb(idport + 1, ptr);
636 outb(idport + 1, ptr);
637
638 if (bootverbose)
639 printf(", Automatic mode");
640 }
641 } else {
642 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
643 outb(idport + 1, pcr);
644 outb(idport + 1, pcr);
645
646 /* configure extended bit in PTR */
647 outb(idport, PC873_PTR);
648 ptr = inb(idport + 1);
649
650 if (chipset_mode & PPB_PS2) {
651 ptr |= PC873_EXTENDED;
652
653 if (bootverbose)
654 printf(", PS/2");
| 601 }
602 }
603 } else {
604 if (bootverbose)
605 printf("PC873xx unlocked");
606
607 if (chipset_mode & PPB_ECP) {
608 if ((chipset_mode & PPB_EPP) && bootverbose)
609 printf(", ECP+EPP not supported");
610
611 pcr &= ~PC873_EPPEN;
612 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
613 outb(idport + 1, pcr);
614 outb(idport + 1, pcr);
615
616 if (bootverbose)
617 printf(", ECP");
618
619 } else if (chipset_mode & PPB_EPP) {
620 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
621 pcr |= (PC873_EPPEN | PC873_EPP19);
622 outb(idport + 1, pcr);
623 outb(idport + 1, pcr);
624
625 ppc->ppc_epp = EPP_1_9; /* XXX */
626
627 if (bootverbose)
628 printf(", EPP1.9");
629
630 /* enable automatic direction turnover */
631 if (ppc->ppc_model == NS_PC87332) {
632 outb(idport, PC873_PTR);
633 ptr = inb(idport + 1);
634 ptr &= ~PC873_EPPRDIR;
635 outb(idport + 1, ptr);
636 outb(idport + 1, ptr);
637
638 if (bootverbose)
639 printf(", Automatic mode");
640 }
641 } else {
642 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
643 outb(idport + 1, pcr);
644 outb(idport + 1, pcr);
645
646 /* configure extended bit in PTR */
647 outb(idport, PC873_PTR);
648 ptr = inb(idport + 1);
649
650 if (chipset_mode & PPB_PS2) {
651 ptr |= PC873_EXTENDED;
652
653 if (bootverbose)
654 printf(", PS/2");
|
655
| 655
|
656 } else {
657 /* default to NIBBLE mode */
658 ptr &= ~PC873_EXTENDED;
659
660 if (bootverbose)
661 printf(", NIBBLE");
662 }
663 outb(idport + 1, ptr);
664 outb(idport + 1, ptr);
665 }
666
667 ppc->ppc_avm = chipset_mode;
668 }
669
670 if (bootverbose)
671 printf("\n");
672
673 ppc->ppc_type = PPC_TYPE_GENERIC;
674 ppc_generic_setmode(ppc, chipset_mode);
675
676 return(chipset_mode);
677 }
678 return(-1);
679}
680
681/*
682 * ppc_smc37c66xgt_detect
683 *
684 * SMC FDC37C66xGT configuration.
685 */
686static int
687ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
688{
689 int s, i;
690 u_char r;
691 int type = -1;
692 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
693
694 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
695
696
697#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
698
699 /*
700 * Detection: enter configuration mode and read CRD register.
701 */
| 656 } else {
657 /* default to NIBBLE mode */
658 ptr &= ~PC873_EXTENDED;
659
660 if (bootverbose)
661 printf(", NIBBLE");
662 }
663 outb(idport + 1, ptr);
664 outb(idport + 1, ptr);
665 }
666
667 ppc->ppc_avm = chipset_mode;
668 }
669
670 if (bootverbose)
671 printf("\n");
672
673 ppc->ppc_type = PPC_TYPE_GENERIC;
674 ppc_generic_setmode(ppc, chipset_mode);
675
676 return(chipset_mode);
677 }
678 return(-1);
679}
680
681/*
682 * ppc_smc37c66xgt_detect
683 *
684 * SMC FDC37C66xGT configuration.
685 */
686static int
687ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
688{
689 int s, i;
690 u_char r;
691 int type = -1;
692 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
693
694 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
695
696
697#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
698
699 /*
700 * Detection: enter configuration mode and read CRD register.
701 */
|
702
| 702
|
703 s = splhigh();
704 outb(csr, SMC665_iCODE);
705 outb(csr, SMC665_iCODE);
706 splx(s);
707
708 outb(csr, 0xd);
709 if (inb(cio) == 0x65) {
710 type = SMC_37C665GT;
711 goto config;
712 }
713
714 for (i = 0; i < 2; i++) {
715 s = splhigh();
716 outb(csr, SMC666_iCODE);
717 outb(csr, SMC666_iCODE);
718 splx(s);
719
720 outb(csr, 0xd);
721 if (inb(cio) == 0x66) {
722 type = SMC_37C666GT;
723 break;
724 }
725
726 /* Another chance, CSR may be hard-configured to be at 0x370 */
727 csr = SMC666_CSR;
728 }
729
730config:
731 /*
732 * If chipset not found, do not continue.
733 */
734 if (type == -1)
735 return (-1);
736
737 /* select CR1 */
738 outb(csr, 0x1);
739
740 /* read the port's address: bits 0 and 1 of CR1 */
741 r = inb(cio) & SMC_CR1_ADDR;
742 if (port_address[(int)r] != ppc->ppc_base)
743 return (-1);
744
745 ppc->ppc_model = type;
746
747 /*
748 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
749 * If SPP mode is detected, try to set ECP+EPP mode
750 */
751
752 if (bootverbose) {
753 outb(csr, 0x1);
754 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
755 inb(cio) & 0xff);
756
757 outb(csr, 0x4);
758 printf(" CR4=0x%x", inb(cio) & 0xff);
759 }
760
761 /* select CR1 */
762 outb(csr, 0x1);
763
764 if (!chipset_mode) {
765 /* autodetect mode */
766
767 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
768 if (type == SMC_37C666GT) {
769 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
770 if (bootverbose)
771 printf(" configuration hardwired, supposing " \
772 "ECP+EPP SPP");
773
774 } else
775 if ((inb(cio) & SMC_CR1_MODE) == 0) {
776 /* already in extended parallel port mode, read CR4 */
777 outb(csr, 0x4);
778 r = (inb(cio) & SMC_CR4_EMODE);
779
780 switch (r) {
781 case SMC_SPP:
782 ppc->ppc_avm |= PPB_SPP;
783 if (bootverbose)
784 printf(" SPP");
785 break;
786
787 case SMC_EPPSPP:
788 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
789 if (bootverbose)
790 printf(" EPP SPP");
791 break;
792
793 case SMC_ECP:
794 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
795 if (bootverbose)
796 printf(" ECP SPP");
797 break;
798
799 case SMC_ECPEPP:
800 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
801 if (bootverbose)
802 printf(" ECP+EPP SPP");
803 break;
804 }
805 } else {
806 /* not an extended port mode */
807 ppc->ppc_avm |= PPB_SPP;
808 if (bootverbose)
809 printf(" SPP");
810 }
811
812 } else {
813 /* mode forced */
814 ppc->ppc_avm = chipset_mode;
815
816 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
817 if (type == SMC_37C666GT)
818 goto end_detect;
819
820 r = inb(cio);
821 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
822 /* do not use ECP when the mode is not forced to */
823 outb(cio, r | SMC_CR1_MODE);
824 if (bootverbose)
825 printf(" SPP");
826 } else {
827 /* an extended mode is selected */
828 outb(cio, r & ~SMC_CR1_MODE);
829
830 /* read CR4 register and reset mode field */
831 outb(csr, 0x4);
832 r = inb(cio) & ~SMC_CR4_EMODE;
833
834 if (chipset_mode & PPB_ECP) {
835 if (chipset_mode & PPB_EPP) {
836 outb(cio, r | SMC_ECPEPP);
837 if (bootverbose)
838 printf(" ECP+EPP");
839 } else {
840 outb(cio, r | SMC_ECP);
841 if (bootverbose)
842 printf(" ECP");
843 }
844 } else {
845 /* PPB_EPP is set */
846 outb(cio, r | SMC_EPPSPP);
847 if (bootverbose)
848 printf(" EPP SPP");
849 }
850 }
851 ppc->ppc_avm = chipset_mode;
852 }
853
854 /* set FIFO threshold to 16 */
855 if (ppc->ppc_avm & PPB_ECP) {
856 /* select CRA */
857 outb(csr, 0xa);
858 outb(cio, 16);
859 }
860
861end_detect:
862
863 if (bootverbose)
864 printf ("\n");
865
866 if (ppc->ppc_avm & PPB_EPP) {
867 /* select CR4 */
868 outb(csr, 0x4);
869 r = inb(cio);
870
871 /*
872 * Set the EPP protocol...
873 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
874 */
875 if (ppc->ppc_epp == EPP_1_9)
876 outb(cio, (r & ~SMC_CR4_EPPTYPE));
877 else
878 outb(cio, (r | SMC_CR4_EPPTYPE));
879 }
880
881 /* end config mode */
882 outb(csr, 0xaa);
883
884 ppc->ppc_type = PPC_TYPE_SMCLIKE;
885 ppc_smclike_setmode(ppc, chipset_mode);
886
887 return (chipset_mode);
888}
889
890/*
891 * SMC FDC37C935 configuration
892 * Found on many Alpha machines
893 */
894static int
895ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
896{
897 int s;
898 int type = -1;
899
900 s = splhigh();
901 outb(SMC935_CFG, 0x55); /* enter config mode */
902 outb(SMC935_CFG, 0x55);
903 splx(s);
904
905 outb(SMC935_IND, SMC935_ID); /* check device id */
906 if (inb(SMC935_DAT) == 0x2)
907 type = SMC_37C935;
908
909 if (type == -1) {
910 outb(SMC935_CFG, 0xaa); /* exit config mode */
911 return (-1);
912 }
913
914 ppc->ppc_model = type;
915
916 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
| 703 s = splhigh();
704 outb(csr, SMC665_iCODE);
705 outb(csr, SMC665_iCODE);
706 splx(s);
707
708 outb(csr, 0xd);
709 if (inb(cio) == 0x65) {
710 type = SMC_37C665GT;
711 goto config;
712 }
713
714 for (i = 0; i < 2; i++) {
715 s = splhigh();
716 outb(csr, SMC666_iCODE);
717 outb(csr, SMC666_iCODE);
718 splx(s);
719
720 outb(csr, 0xd);
721 if (inb(cio) == 0x66) {
722 type = SMC_37C666GT;
723 break;
724 }
725
726 /* Another chance, CSR may be hard-configured to be at 0x370 */
727 csr = SMC666_CSR;
728 }
729
730config:
731 /*
732 * If chipset not found, do not continue.
733 */
734 if (type == -1)
735 return (-1);
736
737 /* select CR1 */
738 outb(csr, 0x1);
739
740 /* read the port's address: bits 0 and 1 of CR1 */
741 r = inb(cio) & SMC_CR1_ADDR;
742 if (port_address[(int)r] != ppc->ppc_base)
743 return (-1);
744
745 ppc->ppc_model = type;
746
747 /*
748 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
749 * If SPP mode is detected, try to set ECP+EPP mode
750 */
751
752 if (bootverbose) {
753 outb(csr, 0x1);
754 device_printf(ppc->ppc_dev, "SMC registers CR1=0x%x",
755 inb(cio) & 0xff);
756
757 outb(csr, 0x4);
758 printf(" CR4=0x%x", inb(cio) & 0xff);
759 }
760
761 /* select CR1 */
762 outb(csr, 0x1);
763
764 if (!chipset_mode) {
765 /* autodetect mode */
766
767 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
768 if (type == SMC_37C666GT) {
769 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
770 if (bootverbose)
771 printf(" configuration hardwired, supposing " \
772 "ECP+EPP SPP");
773
774 } else
775 if ((inb(cio) & SMC_CR1_MODE) == 0) {
776 /* already in extended parallel port mode, read CR4 */
777 outb(csr, 0x4);
778 r = (inb(cio) & SMC_CR4_EMODE);
779
780 switch (r) {
781 case SMC_SPP:
782 ppc->ppc_avm |= PPB_SPP;
783 if (bootverbose)
784 printf(" SPP");
785 break;
786
787 case SMC_EPPSPP:
788 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
789 if (bootverbose)
790 printf(" EPP SPP");
791 break;
792
793 case SMC_ECP:
794 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
795 if (bootverbose)
796 printf(" ECP SPP");
797 break;
798
799 case SMC_ECPEPP:
800 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
801 if (bootverbose)
802 printf(" ECP+EPP SPP");
803 break;
804 }
805 } else {
806 /* not an extended port mode */
807 ppc->ppc_avm |= PPB_SPP;
808 if (bootverbose)
809 printf(" SPP");
810 }
811
812 } else {
813 /* mode forced */
814 ppc->ppc_avm = chipset_mode;
815
816 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
817 if (type == SMC_37C666GT)
818 goto end_detect;
819
820 r = inb(cio);
821 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
822 /* do not use ECP when the mode is not forced to */
823 outb(cio, r | SMC_CR1_MODE);
824 if (bootverbose)
825 printf(" SPP");
826 } else {
827 /* an extended mode is selected */
828 outb(cio, r & ~SMC_CR1_MODE);
829
830 /* read CR4 register and reset mode field */
831 outb(csr, 0x4);
832 r = inb(cio) & ~SMC_CR4_EMODE;
833
834 if (chipset_mode & PPB_ECP) {
835 if (chipset_mode & PPB_EPP) {
836 outb(cio, r | SMC_ECPEPP);
837 if (bootverbose)
838 printf(" ECP+EPP");
839 } else {
840 outb(cio, r | SMC_ECP);
841 if (bootverbose)
842 printf(" ECP");
843 }
844 } else {
845 /* PPB_EPP is set */
846 outb(cio, r | SMC_EPPSPP);
847 if (bootverbose)
848 printf(" EPP SPP");
849 }
850 }
851 ppc->ppc_avm = chipset_mode;
852 }
853
854 /* set FIFO threshold to 16 */
855 if (ppc->ppc_avm & PPB_ECP) {
856 /* select CRA */
857 outb(csr, 0xa);
858 outb(cio, 16);
859 }
860
861end_detect:
862
863 if (bootverbose)
864 printf ("\n");
865
866 if (ppc->ppc_avm & PPB_EPP) {
867 /* select CR4 */
868 outb(csr, 0x4);
869 r = inb(cio);
870
871 /*
872 * Set the EPP protocol...
873 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
874 */
875 if (ppc->ppc_epp == EPP_1_9)
876 outb(cio, (r & ~SMC_CR4_EPPTYPE));
877 else
878 outb(cio, (r | SMC_CR4_EPPTYPE));
879 }
880
881 /* end config mode */
882 outb(csr, 0xaa);
883
884 ppc->ppc_type = PPC_TYPE_SMCLIKE;
885 ppc_smclike_setmode(ppc, chipset_mode);
886
887 return (chipset_mode);
888}
889
890/*
891 * SMC FDC37C935 configuration
892 * Found on many Alpha machines
893 */
894static int
895ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
896{
897 int s;
898 int type = -1;
899
900 s = splhigh();
901 outb(SMC935_CFG, 0x55); /* enter config mode */
902 outb(SMC935_CFG, 0x55);
903 splx(s);
904
905 outb(SMC935_IND, SMC935_ID); /* check device id */
906 if (inb(SMC935_DAT) == 0x2)
907 type = SMC_37C935;
908
909 if (type == -1) {
910 outb(SMC935_CFG, 0xaa); /* exit config mode */
911 return (-1);
912 }
913
914 ppc->ppc_model = type;
915
916 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
|
917 outb(SMC935_DAT, 3); /* which is logical device 3 */
| 917 outb(SMC935_DAT, 3); /* which is logical device 3 */
|
918
919 /* set io port base */
920 outb(SMC935_IND, SMC935_PORTHI);
921 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
922 outb(SMC935_IND, SMC935_PORTLO);
923 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
924
925 if (!chipset_mode)
926 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
927 else {
928 ppc->ppc_avm = chipset_mode;
929 outb(SMC935_IND, SMC935_PPMODE);
930 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
931
932 /* SPP + EPP or just plain SPP */
933 if (chipset_mode & (PPB_SPP)) {
934 if (chipset_mode & PPB_EPP) {
935 if (ppc->ppc_epp == EPP_1_9) {
936 outb(SMC935_IND, SMC935_PPMODE);
937 outb(SMC935_DAT, SMC935_EPP19SPP);
938 }
939 if (ppc->ppc_epp == EPP_1_7) {
940 outb(SMC935_IND, SMC935_PPMODE);
941 outb(SMC935_DAT, SMC935_EPP17SPP);
942 }
943 } else {
944 outb(SMC935_IND, SMC935_PPMODE);
945 outb(SMC935_DAT, SMC935_SPP);
946 }
947 }
948
949 /* ECP + EPP or just plain ECP */
950 if (chipset_mode & PPB_ECP) {
951 if (chipset_mode & PPB_EPP) {
952 if (ppc->ppc_epp == EPP_1_9) {
953 outb(SMC935_IND, SMC935_PPMODE);
954 outb(SMC935_DAT, SMC935_ECPEPP19);
955 }
956 if (ppc->ppc_epp == EPP_1_7) {
957 outb(SMC935_IND, SMC935_PPMODE);
958 outb(SMC935_DAT, SMC935_ECPEPP17);
959 }
960 } else {
961 outb(SMC935_IND, SMC935_PPMODE);
962 outb(SMC935_DAT, SMC935_ECP);
963 }
964 }
965 }
966
967 outb(SMC935_CFG, 0xaa); /* exit config mode */
968
969 ppc->ppc_type = PPC_TYPE_SMCLIKE;
970 ppc_smclike_setmode(ppc, chipset_mode);
971
972 return (chipset_mode);
973}
974
975/*
976 * Winbond W83877F stuff
977 *
978 * EFER: extended function enable register
979 * EFIR: extended function index register
980 * EFDR: extended function data register
981 */
982#define efir ((efer == 0x250) ? 0x251 : 0x3f0)
983#define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
984
985static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
| 918
919 /* set io port base */
920 outb(SMC935_IND, SMC935_PORTHI);
921 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
922 outb(SMC935_IND, SMC935_PORTLO);
923 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
924
925 if (!chipset_mode)
926 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
927 else {
928 ppc->ppc_avm = chipset_mode;
929 outb(SMC935_IND, SMC935_PPMODE);
930 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
931
932 /* SPP + EPP or just plain SPP */
933 if (chipset_mode & (PPB_SPP)) {
934 if (chipset_mode & PPB_EPP) {
935 if (ppc->ppc_epp == EPP_1_9) {
936 outb(SMC935_IND, SMC935_PPMODE);
937 outb(SMC935_DAT, SMC935_EPP19SPP);
938 }
939 if (ppc->ppc_epp == EPP_1_7) {
940 outb(SMC935_IND, SMC935_PPMODE);
941 outb(SMC935_DAT, SMC935_EPP17SPP);
942 }
943 } else {
944 outb(SMC935_IND, SMC935_PPMODE);
945 outb(SMC935_DAT, SMC935_SPP);
946 }
947 }
948
949 /* ECP + EPP or just plain ECP */
950 if (chipset_mode & PPB_ECP) {
951 if (chipset_mode & PPB_EPP) {
952 if (ppc->ppc_epp == EPP_1_9) {
953 outb(SMC935_IND, SMC935_PPMODE);
954 outb(SMC935_DAT, SMC935_ECPEPP19);
955 }
956 if (ppc->ppc_epp == EPP_1_7) {
957 outb(SMC935_IND, SMC935_PPMODE);
958 outb(SMC935_DAT, SMC935_ECPEPP17);
959 }
960 } else {
961 outb(SMC935_IND, SMC935_PPMODE);
962 outb(SMC935_DAT, SMC935_ECP);
963 }
964 }
965 }
966
967 outb(SMC935_CFG, 0xaa); /* exit config mode */
968
969 ppc->ppc_type = PPC_TYPE_SMCLIKE;
970 ppc_smclike_setmode(ppc, chipset_mode);
971
972 return (chipset_mode);
973}
974
975/*
976 * Winbond W83877F stuff
977 *
978 * EFER: extended function enable register
979 * EFIR: extended function index register
980 * EFDR: extended function data register
981 */
982#define efir ((efer == 0x250) ? 0x251 : 0x3f0)
983#define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
984
985static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
|
986static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
| 986static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
|
987static int w83877f_keyiter[] = { 1, 2, 2, 1 };
988static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
989
990static int
991ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
992{
993 int i, j, efer;
994 unsigned char r, hefere, hefras;
995
996 for (i = 0; i < 4; i ++) {
997 /* first try to enable configuration registers */
998 efer = w83877f_efers[i];
999
1000 /* write the key to the EFER */
1001 for (j = 0; j < w83877f_keyiter[i]; j ++)
1002 outb (efer, w83877f_keys[i]);
1003
1004 /* then check HEFERE and HEFRAS bits */
1005 outb (efir, 0x0c);
1006 hefere = inb(efdr) & WINB_HEFERE;
1007
1008 outb (efir, 0x16);
1009 hefras = inb(efdr) & WINB_HEFRAS;
1010
1011 /*
1012 * HEFRAS HEFERE
1013 * 0 1 write 89h to 250h (power-on default)
1014 * 1 0 write 86h twice to 3f0h
1015 * 1 1 write 87h twice to 3f0h
1016 * 0 0 write 88h to 250h
1017 */
1018 if ((hefere | hefras) == w83877f_hefs[i])
1019 goto found;
1020 }
1021
1022 return (-1); /* failed */
1023
1024found:
1025 /* check base port address - read from CR23 */
1026 outb(efir, 0x23);
1027 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1028 return (-1);
1029
1030 /* read CHIP ID from CR9/bits0-3 */
1031 outb(efir, 0x9);
1032
1033 switch (inb(efdr) & WINB_CHIPID) {
1034 case WINB_W83877F_ID:
1035 ppc->ppc_model = WINB_W83877F;
1036 break;
1037
1038 case WINB_W83877AF_ID:
1039 ppc->ppc_model = WINB_W83877AF;
1040 break;
1041
1042 default:
1043 ppc->ppc_model = WINB_UNKNOWN;
1044 }
1045
1046 if (bootverbose) {
1047 /* dump of registers */
1048 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1049 for (i = 0; i <= 0xd; i ++) {
1050 outb(efir, i);
1051 printf("0x%x ", inb(efdr));
1052 }
1053 for (i = 0x10; i <= 0x17; i ++) {
1054 outb(efir, i);
1055 printf("0x%x ", inb(efdr));
1056 }
1057 outb(efir, 0x1e);
1058 printf("0x%x ", inb(efdr));
1059 for (i = 0x20; i <= 0x29; i ++) {
1060 outb(efir, i);
1061 printf("0x%x ", inb(efdr));
1062 }
1063 printf("\n");
1064 }
1065
1066 ppc->ppc_type = PPC_TYPE_GENERIC;
1067
1068 if (!chipset_mode) {
1069 /* autodetect mode */
1070
1071 /* select CR0 */
1072 outb(efir, 0x0);
1073 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1074
1075 /* select CR9 */
1076 outb(efir, 0x9);
1077 r |= (inb(efdr) & WINB_PRTMODS2);
1078
1079 switch (r) {
1080 case WINB_W83757:
1081 if (bootverbose)
1082 device_printf(ppc->ppc_dev,
1083 "W83757 compatible mode\n");
1084 return (-1); /* generic or SMC-like */
1085
1086 case WINB_EXTFDC:
1087 case WINB_EXTADP:
1088 case WINB_EXT2FDD:
1089 case WINB_JOYSTICK:
1090 if (bootverbose)
1091 device_printf(ppc->ppc_dev,
1092 "not in parallel port mode\n");
1093 return (-1);
1094
1095 case (WINB_PARALLEL | WINB_EPP_SPP):
1096 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1097 if (bootverbose)
1098 device_printf(ppc->ppc_dev, "EPP SPP\n");
1099 break;
1100
1101 case (WINB_PARALLEL | WINB_ECP):
1102 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1103 if (bootverbose)
1104 device_printf(ppc->ppc_dev, "ECP SPP\n");
1105 break;
1106
1107 case (WINB_PARALLEL | WINB_ECP_EPP):
1108 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1109 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1110
1111 if (bootverbose)
1112 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1113 break;
1114 default:
1115 printf("%s: unknown case (0x%x)!\n", __func__, r);
1116 }
1117
1118 } else {
1119 /* mode forced */
1120
1121 /* select CR9 and set PRTMODS2 bit */
1122 outb(efir, 0x9);
1123 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1124
1125 /* select CR0 and reset PRTMODSx bits */
1126 outb(efir, 0x0);
1127 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1128
1129 if (chipset_mode & PPB_ECP) {
1130 if (chipset_mode & PPB_EPP) {
1131 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1132 if (bootverbose)
1133 device_printf(ppc->ppc_dev,
1134 "ECP+EPP\n");
1135
1136 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1137
1138 } else {
1139 outb(efdr, inb(efdr) | WINB_ECP);
1140 if (bootverbose)
1141 device_printf(ppc->ppc_dev, "ECP\n");
1142 }
1143 } else {
1144 /* select EPP_SPP otherwise */
1145 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1146 if (bootverbose)
1147 device_printf(ppc->ppc_dev, "EPP SPP\n");
1148 }
1149 ppc->ppc_avm = chipset_mode;
1150 }
1151
1152 /* exit configuration mode */
1153 outb(efer, 0xaa);
1154
1155 switch (ppc->ppc_type) {
1156 case PPC_TYPE_SMCLIKE:
1157 ppc_smclike_setmode(ppc, chipset_mode);
1158 break;
1159 default:
1160 ppc_generic_setmode(ppc, chipset_mode);
1161 break;
1162 }
1163
1164 return (chipset_mode);
1165}
1166#endif
1167
1168/*
1169 * ppc_generic_detect
1170 */
1171static int
1172ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1173{
1174 /* default to generic */
1175 ppc->ppc_type = PPC_TYPE_GENERIC;
1176
1177 if (bootverbose)
1178 device_printf(ppc->ppc_dev, "SPP");
1179
1180 /* first, check for ECP */
1181 w_ecr(ppc, PPC_ECR_PS2);
1182 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1183 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1184 if (bootverbose)
1185 printf(" ECP ");
1186
1187 /* search for SMC style ECP+EPP mode */
1188 w_ecr(ppc, PPC_ECR_EPP);
1189 }
1190
1191 /* try to reset EPP timeout bit */
1192 if (ppc_check_epp_timeout(ppc)) {
1193 ppc->ppc_dtm |= PPB_EPP;
1194
1195 if (ppc->ppc_dtm & PPB_ECP) {
1196 /* SMC like chipset found */
1197 ppc->ppc_model = SMC_LIKE;
1198 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1199
1200 if (bootverbose)
1201 printf(" ECP+EPP");
1202 } else {
1203 if (bootverbose)
1204 printf(" EPP");
1205 }
1206 } else {
1207 /* restore to standard mode */
1208 w_ecr(ppc, PPC_ECR_STD);
1209 }
1210
1211 /* XXX try to detect NIBBLE and PS2 modes */
1212 ppc->ppc_dtm |= PPB_NIBBLE;
1213
1214 if (chipset_mode)
1215 ppc->ppc_avm = chipset_mode;
1216 else
1217 ppc->ppc_avm = ppc->ppc_dtm;
1218
1219 if (bootverbose)
1220 printf("\n");
1221
1222 switch (ppc->ppc_type) {
1223 case PPC_TYPE_SMCLIKE:
1224 ppc_smclike_setmode(ppc, chipset_mode);
1225 break;
1226 default:
1227 ppc_generic_setmode(ppc, chipset_mode);
1228 break;
1229 }
1230
1231 return (chipset_mode);
1232}
1233
1234/*
1235 * ppc_detect()
1236 *
1237 * mode is the mode suggested at boot
1238 */
1239static int
1240ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1241
1242#ifdef PPC_PROBE_CHIPSET
1243 int i, mode;
1244
1245 /* list of supported chipsets */
1246 int (*chipset_detect[])(struct ppc_data *, int) = {
1247 ppc_pc873xx_detect,
1248 ppc_smc37c66xgt_detect,
1249 ppc_w83877f_detect,
1250 ppc_smc37c935_detect,
1251 ppc_generic_detect,
1252 NULL
1253 };
1254#endif
1255
1256 /* if can't find the port and mode not forced return error */
1257 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1258 return (EIO); /* failed, port not present */
1259
1260 /* assume centronics compatible mode is supported */
1261 ppc->ppc_avm = PPB_COMPATIBLE;
1262
1263#ifdef PPC_PROBE_CHIPSET
1264 /* we have to differenciate available chipset modes,
1265 * chipset running modes and IEEE-1284 operating modes
1266 *
1267 * after detection, the port must support running in compatible mode
1268 */
1269 if (ppc->ppc_flags & 0x40) {
1270 if (bootverbose)
1271 printf("ppc: chipset forced to generic\n");
1272#endif
1273
1274 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1275
1276#ifdef PPC_PROBE_CHIPSET
1277 } else {
1278 for (i=0; chipset_detect[i] != NULL; i++) {
1279 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1280 ppc->ppc_mode = mode;
1281 break;
1282 }
1283 }
1284 }
1285#endif
1286
1287 /* configure/detect ECP FIFO */
1288 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1289 ppc_detect_fifo(ppc);
1290
1291 return (0);
1292}
1293
1294/*
1295 * ppc_exec_microseq()
1296 *
1297 * Execute a microsequence.
1298 * Microsequence mechanism is supposed to handle fast I/O operations.
1299 */
1300int
1301ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1302{
1303 struct ppc_data *ppc = DEVTOSOFTC(dev);
1304 struct ppb_microseq *mi;
1305 char cc, *p;
1306 int i, iter, len;
1307 int error;
1308
1309 register int reg;
1310 register char mask;
1311 register int accum = 0;
1312 register char *ptr = 0;
1313
1314 struct ppb_microseq *stack = 0;
1315
1316/* microsequence registers are equivalent to PC-like port registers */
1317
1318#define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1319#define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1320
1321#define INCR_PC (mi ++) /* increment program counter */
1322
1323 mi = *p_msq;
1324 for (;;) {
| 987static int w83877f_keyiter[] = { 1, 2, 2, 1 };
988static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
989
990static int
991ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
992{
993 int i, j, efer;
994 unsigned char r, hefere, hefras;
995
996 for (i = 0; i < 4; i ++) {
997 /* first try to enable configuration registers */
998 efer = w83877f_efers[i];
999
1000 /* write the key to the EFER */
1001 for (j = 0; j < w83877f_keyiter[i]; j ++)
1002 outb (efer, w83877f_keys[i]);
1003
1004 /* then check HEFERE and HEFRAS bits */
1005 outb (efir, 0x0c);
1006 hefere = inb(efdr) & WINB_HEFERE;
1007
1008 outb (efir, 0x16);
1009 hefras = inb(efdr) & WINB_HEFRAS;
1010
1011 /*
1012 * HEFRAS HEFERE
1013 * 0 1 write 89h to 250h (power-on default)
1014 * 1 0 write 86h twice to 3f0h
1015 * 1 1 write 87h twice to 3f0h
1016 * 0 0 write 88h to 250h
1017 */
1018 if ((hefere | hefras) == w83877f_hefs[i])
1019 goto found;
1020 }
1021
1022 return (-1); /* failed */
1023
1024found:
1025 /* check base port address - read from CR23 */
1026 outb(efir, 0x23);
1027 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1028 return (-1);
1029
1030 /* read CHIP ID from CR9/bits0-3 */
1031 outb(efir, 0x9);
1032
1033 switch (inb(efdr) & WINB_CHIPID) {
1034 case WINB_W83877F_ID:
1035 ppc->ppc_model = WINB_W83877F;
1036 break;
1037
1038 case WINB_W83877AF_ID:
1039 ppc->ppc_model = WINB_W83877AF;
1040 break;
1041
1042 default:
1043 ppc->ppc_model = WINB_UNKNOWN;
1044 }
1045
1046 if (bootverbose) {
1047 /* dump of registers */
1048 device_printf(ppc->ppc_dev, "0x%x - ", w83877f_keys[i]);
1049 for (i = 0; i <= 0xd; i ++) {
1050 outb(efir, i);
1051 printf("0x%x ", inb(efdr));
1052 }
1053 for (i = 0x10; i <= 0x17; i ++) {
1054 outb(efir, i);
1055 printf("0x%x ", inb(efdr));
1056 }
1057 outb(efir, 0x1e);
1058 printf("0x%x ", inb(efdr));
1059 for (i = 0x20; i <= 0x29; i ++) {
1060 outb(efir, i);
1061 printf("0x%x ", inb(efdr));
1062 }
1063 printf("\n");
1064 }
1065
1066 ppc->ppc_type = PPC_TYPE_GENERIC;
1067
1068 if (!chipset_mode) {
1069 /* autodetect mode */
1070
1071 /* select CR0 */
1072 outb(efir, 0x0);
1073 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1074
1075 /* select CR9 */
1076 outb(efir, 0x9);
1077 r |= (inb(efdr) & WINB_PRTMODS2);
1078
1079 switch (r) {
1080 case WINB_W83757:
1081 if (bootverbose)
1082 device_printf(ppc->ppc_dev,
1083 "W83757 compatible mode\n");
1084 return (-1); /* generic or SMC-like */
1085
1086 case WINB_EXTFDC:
1087 case WINB_EXTADP:
1088 case WINB_EXT2FDD:
1089 case WINB_JOYSTICK:
1090 if (bootverbose)
1091 device_printf(ppc->ppc_dev,
1092 "not in parallel port mode\n");
1093 return (-1);
1094
1095 case (WINB_PARALLEL | WINB_EPP_SPP):
1096 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1097 if (bootverbose)
1098 device_printf(ppc->ppc_dev, "EPP SPP\n");
1099 break;
1100
1101 case (WINB_PARALLEL | WINB_ECP):
1102 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1103 if (bootverbose)
1104 device_printf(ppc->ppc_dev, "ECP SPP\n");
1105 break;
1106
1107 case (WINB_PARALLEL | WINB_ECP_EPP):
1108 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1109 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1110
1111 if (bootverbose)
1112 device_printf(ppc->ppc_dev, "ECP+EPP SPP\n");
1113 break;
1114 default:
1115 printf("%s: unknown case (0x%x)!\n", __func__, r);
1116 }
1117
1118 } else {
1119 /* mode forced */
1120
1121 /* select CR9 and set PRTMODS2 bit */
1122 outb(efir, 0x9);
1123 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1124
1125 /* select CR0 and reset PRTMODSx bits */
1126 outb(efir, 0x0);
1127 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1128
1129 if (chipset_mode & PPB_ECP) {
1130 if (chipset_mode & PPB_EPP) {
1131 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1132 if (bootverbose)
1133 device_printf(ppc->ppc_dev,
1134 "ECP+EPP\n");
1135
1136 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1137
1138 } else {
1139 outb(efdr, inb(efdr) | WINB_ECP);
1140 if (bootverbose)
1141 device_printf(ppc->ppc_dev, "ECP\n");
1142 }
1143 } else {
1144 /* select EPP_SPP otherwise */
1145 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1146 if (bootverbose)
1147 device_printf(ppc->ppc_dev, "EPP SPP\n");
1148 }
1149 ppc->ppc_avm = chipset_mode;
1150 }
1151
1152 /* exit configuration mode */
1153 outb(efer, 0xaa);
1154
1155 switch (ppc->ppc_type) {
1156 case PPC_TYPE_SMCLIKE:
1157 ppc_smclike_setmode(ppc, chipset_mode);
1158 break;
1159 default:
1160 ppc_generic_setmode(ppc, chipset_mode);
1161 break;
1162 }
1163
1164 return (chipset_mode);
1165}
1166#endif
1167
1168/*
1169 * ppc_generic_detect
1170 */
1171static int
1172ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1173{
1174 /* default to generic */
1175 ppc->ppc_type = PPC_TYPE_GENERIC;
1176
1177 if (bootverbose)
1178 device_printf(ppc->ppc_dev, "SPP");
1179
1180 /* first, check for ECP */
1181 w_ecr(ppc, PPC_ECR_PS2);
1182 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1183 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1184 if (bootverbose)
1185 printf(" ECP ");
1186
1187 /* search for SMC style ECP+EPP mode */
1188 w_ecr(ppc, PPC_ECR_EPP);
1189 }
1190
1191 /* try to reset EPP timeout bit */
1192 if (ppc_check_epp_timeout(ppc)) {
1193 ppc->ppc_dtm |= PPB_EPP;
1194
1195 if (ppc->ppc_dtm & PPB_ECP) {
1196 /* SMC like chipset found */
1197 ppc->ppc_model = SMC_LIKE;
1198 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1199
1200 if (bootverbose)
1201 printf(" ECP+EPP");
1202 } else {
1203 if (bootverbose)
1204 printf(" EPP");
1205 }
1206 } else {
1207 /* restore to standard mode */
1208 w_ecr(ppc, PPC_ECR_STD);
1209 }
1210
1211 /* XXX try to detect NIBBLE and PS2 modes */
1212 ppc->ppc_dtm |= PPB_NIBBLE;
1213
1214 if (chipset_mode)
1215 ppc->ppc_avm = chipset_mode;
1216 else
1217 ppc->ppc_avm = ppc->ppc_dtm;
1218
1219 if (bootverbose)
1220 printf("\n");
1221
1222 switch (ppc->ppc_type) {
1223 case PPC_TYPE_SMCLIKE:
1224 ppc_smclike_setmode(ppc, chipset_mode);
1225 break;
1226 default:
1227 ppc_generic_setmode(ppc, chipset_mode);
1228 break;
1229 }
1230
1231 return (chipset_mode);
1232}
1233
1234/*
1235 * ppc_detect()
1236 *
1237 * mode is the mode suggested at boot
1238 */
1239static int
1240ppc_detect(struct ppc_data *ppc, int chipset_mode) {
1241
1242#ifdef PPC_PROBE_CHIPSET
1243 int i, mode;
1244
1245 /* list of supported chipsets */
1246 int (*chipset_detect[])(struct ppc_data *, int) = {
1247 ppc_pc873xx_detect,
1248 ppc_smc37c66xgt_detect,
1249 ppc_w83877f_detect,
1250 ppc_smc37c935_detect,
1251 ppc_generic_detect,
1252 NULL
1253 };
1254#endif
1255
1256 /* if can't find the port and mode not forced return error */
1257 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1258 return (EIO); /* failed, port not present */
1259
1260 /* assume centronics compatible mode is supported */
1261 ppc->ppc_avm = PPB_COMPATIBLE;
1262
1263#ifdef PPC_PROBE_CHIPSET
1264 /* we have to differenciate available chipset modes,
1265 * chipset running modes and IEEE-1284 operating modes
1266 *
1267 * after detection, the port must support running in compatible mode
1268 */
1269 if (ppc->ppc_flags & 0x40) {
1270 if (bootverbose)
1271 printf("ppc: chipset forced to generic\n");
1272#endif
1273
1274 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1275
1276#ifdef PPC_PROBE_CHIPSET
1277 } else {
1278 for (i=0; chipset_detect[i] != NULL; i++) {
1279 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1280 ppc->ppc_mode = mode;
1281 break;
1282 }
1283 }
1284 }
1285#endif
1286
1287 /* configure/detect ECP FIFO */
1288 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1289 ppc_detect_fifo(ppc);
1290
1291 return (0);
1292}
1293
1294/*
1295 * ppc_exec_microseq()
1296 *
1297 * Execute a microsequence.
1298 * Microsequence mechanism is supposed to handle fast I/O operations.
1299 */
1300int
1301ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1302{
1303 struct ppc_data *ppc = DEVTOSOFTC(dev);
1304 struct ppb_microseq *mi;
1305 char cc, *p;
1306 int i, iter, len;
1307 int error;
1308
1309 register int reg;
1310 register char mask;
1311 register int accum = 0;
1312 register char *ptr = 0;
1313
1314 struct ppb_microseq *stack = 0;
1315
1316/* microsequence registers are equivalent to PC-like port registers */
1317
1318#define r_reg(reg,ppc) (bus_read_1((ppc)->res_ioport, reg))
1319#define w_reg(reg, ppc, byte) (bus_write_1((ppc)->res_ioport, reg, byte))
1320
1321#define INCR_PC (mi ++) /* increment program counter */
1322
1323 mi = *p_msq;
1324 for (;;) {
|
1325 switch (mi->opcode) {
| 1325 switch (mi->opcode) {
|
1326 case MS_OP_RSET:
1327 cc = r_reg(mi->arg[0].i, ppc);
1328 cc &= (char)mi->arg[2].i; /* clear mask */
1329 cc |= (char)mi->arg[1].i; /* assert mask */
| 1326 case MS_OP_RSET:
1327 cc = r_reg(mi->arg[0].i, ppc);
1328 cc &= (char)mi->arg[2].i; /* clear mask */
1329 cc |= (char)mi->arg[1].i; /* assert mask */
|
1330 w_reg(mi->arg[0].i, ppc, cc);
| 1330 w_reg(mi->arg[0].i, ppc, cc);
|
1331 INCR_PC;
| 1331 INCR_PC;
|
1332 break;
| 1332 break;
|
1333
1334 case MS_OP_RASSERT_P:
1335 reg = mi->arg[1].i;
1336 ptr = ppc->ppc_ptr;
1337
1338 if ((len = mi->arg[0].i) == MS_ACCUM) {
1339 accum = ppc->ppc_accum;
1340 for (; accum; accum--)
1341 w_reg(reg, ppc, *ptr++);
1342 ppc->ppc_accum = accum;
1343 } else
1344 for (i=0; i<len; i++)
1345 w_reg(reg, ppc, *ptr++);
1346 ppc->ppc_ptr = ptr;
1347
1348 INCR_PC;
1349 break;
1350
| 1333
1334 case MS_OP_RASSERT_P:
1335 reg = mi->arg[1].i;
1336 ptr = ppc->ppc_ptr;
1337
1338 if ((len = mi->arg[0].i) == MS_ACCUM) {
1339 accum = ppc->ppc_accum;
1340 for (; accum; accum--)
1341 w_reg(reg, ppc, *ptr++);
1342 ppc->ppc_accum = accum;
1343 } else
1344 for (i=0; i<len; i++)
1345 w_reg(reg, ppc, *ptr++);
1346 ppc->ppc_ptr = ptr;
1347
1348 INCR_PC;
1349 break;
1350
|
1351 case MS_OP_RFETCH_P:
| 1351 case MS_OP_RFETCH_P:
|
1352 reg = mi->arg[1].i;
1353 mask = (char)mi->arg[2].i;
1354 ptr = ppc->ppc_ptr;
1355
1356 if ((len = mi->arg[0].i) == MS_ACCUM) {
1357 accum = ppc->ppc_accum;
1358 for (; accum; accum--)
1359 *ptr++ = r_reg(reg, ppc) & mask;
1360 ppc->ppc_accum = accum;
1361 } else
1362 for (i=0; i<len; i++)
1363 *ptr++ = r_reg(reg, ppc) & mask;
1364 ppc->ppc_ptr = ptr;
1365
1366 INCR_PC;
| 1352 reg = mi->arg[1].i;
1353 mask = (char)mi->arg[2].i;
1354 ptr = ppc->ppc_ptr;
1355
1356 if ((len = mi->arg[0].i) == MS_ACCUM) {
1357 accum = ppc->ppc_accum;
1358 for (; accum; accum--)
1359 *ptr++ = r_reg(reg, ppc) & mask;
1360 ppc->ppc_accum = accum;
1361 } else
1362 for (i=0; i<len; i++)
1363 *ptr++ = r_reg(reg, ppc) & mask;
1364 ppc->ppc_ptr = ptr;
1365
1366 INCR_PC;
|
1367 break;
| 1367 break;
|
1368
| 1368
|
1369 case MS_OP_RFETCH:
| 1369 case MS_OP_RFETCH:
|
1370 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1371 (char)mi->arg[1].i;
1372 INCR_PC;
| 1370 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1371 (char)mi->arg[1].i;
1372 INCR_PC;
|
1373 break;
| 1373 break;
|
1374
1375 case MS_OP_RASSERT:
| 1374
1375 case MS_OP_RASSERT:
|
1376 case MS_OP_DELAY:
1377
| 1376 case MS_OP_DELAY:
1377
|
1378 /* let's suppose the next instr. is the same */
1379 prefetch:
1380 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1381 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1382
1383 if (mi->opcode == MS_OP_DELAY) {
1384 DELAY(mi->arg[0].i);
1385 INCR_PC;
1386 goto prefetch;
1387 }
1388 break;
1389
1390 case MS_OP_ADELAY:
1391 if (mi->arg[0].i)
1392 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1393 INCR_PC;
1394 break;
1395
1396 case MS_OP_TRIG:
1397 reg = mi->arg[0].i;
1398 iter = mi->arg[1].i;
1399 p = (char *)mi->arg[2].p;
1400
1401 /* XXX delay limited to 255 us */
1402 for (i=0; i<iter; i++) {
1403 w_reg(reg, ppc, *p++);
1404 DELAY((unsigned char)*p++);
1405 }
1406 INCR_PC;
1407 break;
1408
| 1378 /* let's suppose the next instr. is the same */
1379 prefetch:
1380 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1381 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1382
1383 if (mi->opcode == MS_OP_DELAY) {
1384 DELAY(mi->arg[0].i);
1385 INCR_PC;
1386 goto prefetch;
1387 }
1388 break;
1389
1390 case MS_OP_ADELAY:
1391 if (mi->arg[0].i)
1392 pause("ppbdelay", mi->arg[0].i * (hz/1000));
1393 INCR_PC;
1394 break;
1395
1396 case MS_OP_TRIG:
1397 reg = mi->arg[0].i;
1398 iter = mi->arg[1].i;
1399 p = (char *)mi->arg[2].p;
1400
1401 /* XXX delay limited to 255 us */
1402 for (i=0; i<iter; i++) {
1403 w_reg(reg, ppc, *p++);
1404 DELAY((unsigned char)*p++);
1405 }
1406 INCR_PC;
1407 break;
1408
|
1409 case MS_OP_SET:
1410 ppc->ppc_accum = mi->arg[0].i;
| 1409 case MS_OP_SET:
1410 ppc->ppc_accum = mi->arg[0].i;
|
1411 INCR_PC;
| 1411 INCR_PC;
|
1412 break;
| 1412 break;
|
1413
| 1413
|
1414 case MS_OP_DBRA:
1415 if (--ppc->ppc_accum > 0)
1416 mi += mi->arg[0].i;
| 1414 case MS_OP_DBRA:
1415 if (--ppc->ppc_accum > 0)
1416 mi += mi->arg[0].i;
|
1417 INCR_PC;
| 1417 INCR_PC;
|
1418 break;
| 1418 break;
|
1419
| 1419
|
1420 case MS_OP_BRSET:
1421 cc = r_str(ppc);
1422 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1423 mi += mi->arg[1].i;
| 1420 case MS_OP_BRSET:
1421 cc = r_str(ppc);
1422 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1423 mi += mi->arg[1].i;
|
1424 INCR_PC;
| 1424 INCR_PC;
|
1425 break;
| 1425 break;
|
1426
| 1426
|
1427 case MS_OP_BRCLEAR:
1428 cc = r_str(ppc);
1429 if ((cc & (char)mi->arg[0].i) == 0)
1430 mi += mi->arg[1].i;
| 1427 case MS_OP_BRCLEAR:
1428 cc = r_str(ppc);
1429 if ((cc & (char)mi->arg[0].i) == 0)
1430 mi += mi->arg[1].i;
|
1431 INCR_PC;
| 1431 INCR_PC;
|
1432 break;
| 1432 break;
|
1433
1434 case MS_OP_BRSTAT:
1435 cc = r_str(ppc);
1436 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1437 (char)mi->arg[0].i)
1438 mi += mi->arg[2].i;
1439 INCR_PC;
1440 break;
1441
1442 case MS_OP_C_CALL:
1443 /*
1444 * If the C call returns !0 then end the microseq.
1445 * The current state of ptr is passed to the C function
1446 */
1447 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1448 return (error);
1449
1450 INCR_PC;
1451 break;
1452
1453 case MS_OP_PTR:
1454 ppc->ppc_ptr = (char *)mi->arg[0].p;
1455 INCR_PC;
1456 break;
1457
1458 case MS_OP_CALL:
1459 if (stack)
1460 panic("%s: too much calls", __func__);
1461
1462 if (mi->arg[0].p) {
1463 /* store the state of the actual
1464 * microsequence
1465 */
1466 stack = mi;
1467
1468 /* jump to the new microsequence */
1469 mi = (struct ppb_microseq *)mi->arg[0].p;
1470 } else
1471 INCR_PC;
1472
1473 break;
1474
1475 case MS_OP_SUBRET:
1476 /* retrieve microseq and pc state before the call */
1477 mi = stack;
1478
1479 /* reset the stack */
1480 stack = 0;
1481
1482 /* XXX return code */
1483
1484 INCR_PC;
1485 break;
1486
| 1433
1434 case MS_OP_BRSTAT:
1435 cc = r_str(ppc);
1436 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1437 (char)mi->arg[0].i)
1438 mi += mi->arg[2].i;
1439 INCR_PC;
1440 break;
1441
1442 case MS_OP_C_CALL:
1443 /*
1444 * If the C call returns !0 then end the microseq.
1445 * The current state of ptr is passed to the C function
1446 */
1447 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1448 return (error);
1449
1450 INCR_PC;
1451 break;
1452
1453 case MS_OP_PTR:
1454 ppc->ppc_ptr = (char *)mi->arg[0].p;
1455 INCR_PC;
1456 break;
1457
1458 case MS_OP_CALL:
1459 if (stack)
1460 panic("%s: too much calls", __func__);
1461
1462 if (mi->arg[0].p) {
1463 /* store the state of the actual
1464 * microsequence
1465 */
1466 stack = mi;
1467
1468 /* jump to the new microsequence */
1469 mi = (struct ppb_microseq *)mi->arg[0].p;
1470 } else
1471 INCR_PC;
1472
1473 break;
1474
1475 case MS_OP_SUBRET:
1476 /* retrieve microseq and pc state before the call */
1477 mi = stack;
1478
1479 /* reset the stack */
1480 stack = 0;
1481
1482 /* XXX return code */
1483
1484 INCR_PC;
1485 break;
1486
|
1487 case MS_OP_PUT:
1488 case MS_OP_GET:
1489 case MS_OP_RET:
| 1487 case MS_OP_PUT:
1488 case MS_OP_GET:
1489 case MS_OP_RET:
|
1490 /* can't return to ppb level during the execution
1491 * of a submicrosequence */
1492 if (stack)
1493 panic("%s: can't return to ppb level",
1494 __func__);
1495
1496 /* update pc for ppb level of execution */
1497 *p_msq = mi;
1498
1499 /* return to ppb level of execution */
1500 return (0);
1501
| 1490 /* can't return to ppb level during the execution
1491 * of a submicrosequence */
1492 if (stack)
1493 panic("%s: can't return to ppb level",
1494 __func__);
1495
1496 /* update pc for ppb level of execution */
1497 *p_msq = mi;
1498
1499 /* return to ppb level of execution */
1500 return (0);
1501
|
1502 default:
1503 panic("%s: unknown microsequence opcode 0x%x",
1504 __func__, mi->opcode);
1505 }
| 1502 default:
1503 panic("%s: unknown microsequence opcode 0x%x",
1504 __func__, mi->opcode);
1505 }
|
1506 }
1507
1508 /* unreached */
1509}
1510
1511static void
1512ppcintr(void *arg)
1513{
1514 struct ppc_data *ppc = arg;
1515 u_char ctr, ecr, str;
1516
1517 /*
1518 * If we have any child interrupt handlers registered, let
1519 * them handle this interrupt.
1520 *
1521 * XXX: If DMA is in progress should we just complete that w/o
1522 * doing this?
1523 */
1524 if (ppc->ppc_child_handlers > 0) {
1525 intr_event_execute_handlers(curproc, ppc->ppc_intr_event);
1526 return;
1527 }
1528
1529 str = r_str(ppc);
1530 ctr = r_ctr(ppc);
1531 ecr = r_ecr(ppc);
1532
1533#if defined(PPC_DEBUG) && PPC_DEBUG > 1
1534 printf("![%x/%x/%x]", ctr, ecr, str);
1535#endif
1536
1537 /* don't use ecp mode with IRQENABLE set */
1538 if (ctr & IRQENABLE) {
1539 return;
1540 }
1541
1542 /* interrupts are generated by nFault signal
1543 * only in ECP mode */
1544 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1545 /* check if ppc driver has programmed the
1546 * nFault interrupt */
1547 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1548
1549 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1550 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1551 } else {
1552 /* shall be handled by underlying layers XXX */
1553 return;
1554 }
1555 }
1556
1557 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1558 /* disable interrupts (should be done by hardware though) */
1559 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1560 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1561 ecr = r_ecr(ppc);
1562
1563 /* check if DMA completed */
1564 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1565#ifdef PPC_DEBUG
1566 printf("a");
1567#endif
1568 /* stop DMA */
1569 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1570 ecr = r_ecr(ppc);
1571
1572 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1573#ifdef PPC_DEBUG
1574 printf("d");
1575#endif
1576 ppc->ppc_dmadone(ppc);
1577 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1578
1579 /* wakeup the waiting process */
1580 wakeup(ppc);
1581 }
1582 }
1583 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1584
1585 /* classic interrupt I/O */
1586 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1587 }
1588
1589 return;
1590}
1591
1592int
1593ppc_read(device_t dev, char *buf, int len, int mode)
1594{
1595 return (EINVAL);
1596}
1597
1598int
1599ppc_write(device_t dev, char *buf, int len, int how)
1600{
1601 return (EINVAL);
1602}
1603
1604void
1605ppc_reset_epp(device_t dev)
1606{
1607 struct ppc_data *ppc = DEVTOSOFTC(dev);
| 1506 }
1507
1508 /* unreached */
1509}
1510
1511static void
1512ppcintr(void *arg)
1513{
1514 struct ppc_data *ppc = arg;
1515 u_char ctr, ecr, str;
1516
1517 /*
1518 * If we have any child interrupt handlers registered, let
1519 * them handle this interrupt.
1520 *
1521 * XXX: If DMA is in progress should we just complete that w/o
1522 * doing this?
1523 */
1524 if (ppc->ppc_child_handlers > 0) {
1525 intr_event_execute_handlers(curproc, ppc->ppc_intr_event);
1526 return;
1527 }
1528
1529 str = r_str(ppc);
1530 ctr = r_ctr(ppc);
1531 ecr = r_ecr(ppc);
1532
1533#if defined(PPC_DEBUG) && PPC_DEBUG > 1
1534 printf("![%x/%x/%x]", ctr, ecr, str);
1535#endif
1536
1537 /* don't use ecp mode with IRQENABLE set */
1538 if (ctr & IRQENABLE) {
1539 return;
1540 }
1541
1542 /* interrupts are generated by nFault signal
1543 * only in ECP mode */
1544 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1545 /* check if ppc driver has programmed the
1546 * nFault interrupt */
1547 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1548
1549 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1550 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1551 } else {
1552 /* shall be handled by underlying layers XXX */
1553 return;
1554 }
1555 }
1556
1557 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1558 /* disable interrupts (should be done by hardware though) */
1559 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1560 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1561 ecr = r_ecr(ppc);
1562
1563 /* check if DMA completed */
1564 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1565#ifdef PPC_DEBUG
1566 printf("a");
1567#endif
1568 /* stop DMA */
1569 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1570 ecr = r_ecr(ppc);
1571
1572 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1573#ifdef PPC_DEBUG
1574 printf("d");
1575#endif
1576 ppc->ppc_dmadone(ppc);
1577 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1578
1579 /* wakeup the waiting process */
1580 wakeup(ppc);
1581 }
1582 }
1583 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1584
1585 /* classic interrupt I/O */
1586 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1587 }
1588
1589 return;
1590}
1591
1592int
1593ppc_read(device_t dev, char *buf, int len, int mode)
1594{
1595 return (EINVAL);
1596}
1597
1598int
1599ppc_write(device_t dev, char *buf, int len, int how)
1600{
1601 return (EINVAL);
1602}
1603
1604void
1605ppc_reset_epp(device_t dev)
1606{
1607 struct ppc_data *ppc = DEVTOSOFTC(dev);
|
1608
| 1608
|
1609 ppc_reset_epp_timeout(ppc);
1610
1611 return;
1612}
1613
1614int
1615ppc_setmode(device_t dev, int mode)
1616{
1617 struct ppc_data *ppc = DEVTOSOFTC(dev);
1618
1619 switch (ppc->ppc_type) {
1620 case PPC_TYPE_SMCLIKE:
1621 return (ppc_smclike_setmode(ppc, mode));
1622 break;
1623
1624 case PPC_TYPE_GENERIC:
1625 default:
1626 return (ppc_generic_setmode(ppc, mode));
1627 break;
1628 }
1629
1630 /* not reached */
1631 return (ENXIO);
1632}
1633
1634int
1635ppc_probe(device_t dev, int rid)
1636{
1637#ifdef __i386__
1638 static short next_bios_ppc = 0;
1639#ifdef PC98
1640 unsigned int pc98_ieee_mode = 0x00;
1641 unsigned int tmp;
1642#endif
1643#endif
1644 struct ppc_data *ppc;
1645 int error;
1646 u_long port;
1647
1648 /*
1649 * Allocate the ppc_data structure.
1650 */
1651 ppc = DEVTOSOFTC(dev);
1652 bzero(ppc, sizeof(struct ppc_data));
1653
1654 ppc->rid_ioport = rid;
1655
1656 /* retrieve ISA parameters */
1657 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1658
1659#ifdef __i386__
1660 /*
1661 * If port not specified, use bios list.
1662 */
1663 if (error) {
1664#ifdef PC98
1665 if (next_bios_ppc == 0) {
1666 /* Use default IEEE-1284 port of NEC PC-98x1 */
1667 port = PC98_IEEE_1284_PORT;
1668 next_bios_ppc += 1;
1669 if (bootverbose)
1670 device_printf(dev,
| 1609 ppc_reset_epp_timeout(ppc);
1610
1611 return;
1612}
1613
1614int
1615ppc_setmode(device_t dev, int mode)
1616{
1617 struct ppc_data *ppc = DEVTOSOFTC(dev);
1618
1619 switch (ppc->ppc_type) {
1620 case PPC_TYPE_SMCLIKE:
1621 return (ppc_smclike_setmode(ppc, mode));
1622 break;
1623
1624 case PPC_TYPE_GENERIC:
1625 default:
1626 return (ppc_generic_setmode(ppc, mode));
1627 break;
1628 }
1629
1630 /* not reached */
1631 return (ENXIO);
1632}
1633
1634int
1635ppc_probe(device_t dev, int rid)
1636{
1637#ifdef __i386__
1638 static short next_bios_ppc = 0;
1639#ifdef PC98
1640 unsigned int pc98_ieee_mode = 0x00;
1641 unsigned int tmp;
1642#endif
1643#endif
1644 struct ppc_data *ppc;
1645 int error;
1646 u_long port;
1647
1648 /*
1649 * Allocate the ppc_data structure.
1650 */
1651 ppc = DEVTOSOFTC(dev);
1652 bzero(ppc, sizeof(struct ppc_data));
1653
1654 ppc->rid_ioport = rid;
1655
1656 /* retrieve ISA parameters */
1657 error = bus_get_resource(dev, SYS_RES_IOPORT, rid, &port, NULL);
1658
1659#ifdef __i386__
1660 /*
1661 * If port not specified, use bios list.
1662 */
1663 if (error) {
1664#ifdef PC98
1665 if (next_bios_ppc == 0) {
1666 /* Use default IEEE-1284 port of NEC PC-98x1 */
1667 port = PC98_IEEE_1284_PORT;
1668 next_bios_ppc += 1;
1669 if (bootverbose)
1670 device_printf(dev,
|
1671 "parallel port found at 0x%x\n",
1672 (int) port);
| 1671 "parallel port found at 0x%lx\n", port);
|
1673 }
1674#else
| 1672 }
1673#else
|
1675 if((next_bios_ppc < BIOS_MAX_PPC) &&
1676 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1677 port = *(BIOS_PORTS+next_bios_ppc++);
| 1674 if ((next_bios_ppc < BIOS_MAX_PPC) &&
1675 (*(BIOS_PORTS + next_bios_ppc) != 0)) {
1676 port = *(BIOS_PORTS + next_bios_ppc++);
|
1678 if (bootverbose)
| 1677 if (bootverbose)
|
1679 device_printf(dev, "parallel port found at 0x%x\n",
1680 (int) port);
| 1678 device_printf(dev,
1679 "parallel port found at 0x%lx\n", port);
|
1681 } else {
1682 device_printf(dev, "parallel port not found.\n");
| 1680 } else {
1681 device_printf(dev, "parallel port not found.\n");
|
1683 return ENXIO;
| 1682 return (ENXIO);
|
1684 }
1685#endif /* PC98 */
1686 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1687 IO_LPTSIZE_EXTENDED);
1688 }
1689#endif
1690
1691 /* IO port is mandatory */
1692
1693 /* Try "extended" IO port range...*/
1694 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1695 &ppc->rid_ioport, 0, ~0,
1696 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1697
1698 if (ppc->res_ioport != 0) {
1699 if (bootverbose)
1700 device_printf(dev, "using extended I/O port range\n");
1701 } else {
1702 /* Failed? If so, then try the "normal" IO port range... */
1703 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1704 &ppc->rid_ioport, 0, ~0,
1705 IO_LPTSIZE_NORMAL,
1706 RF_ACTIVE);
1707 if (ppc->res_ioport != 0) {
1708 if (bootverbose)
1709 device_printf(dev, "using normal I/O port range\n");
1710 } else {
1711 device_printf(dev, "cannot reserve I/O port range\n");
1712 goto error;
1713 }
1714 }
1715
1716 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1717
1718 ppc->ppc_flags = device_get_flags(dev);
1719
1720 if (!(ppc->ppc_flags & 0x20)) {
1721 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1722 &ppc->rid_irq,
1723 RF_SHAREABLE);
1724 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1725 &ppc->rid_drq,
1726 RF_ACTIVE);
1727 }
1728
1729 if (ppc->res_irq)
1730 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1731 if (ppc->res_drq)
1732 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1733
1734 ppc->ppc_dev = dev;
1735 ppc->ppc_model = GENERIC;
1736
1737 ppc->ppc_mode = PPB_COMPATIBLE;
1738 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1739
1740 ppc->ppc_type = PPC_TYPE_GENERIC;
1741
1742#if defined(__i386__) && defined(PC98)
1743 /*
1744 * IEEE STD 1284 Function Check and Enable
1745 * for default IEEE-1284 port of NEC PC-98x1
1746 */
1747 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1748 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1749 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1750 pc98_ieee_mode = tmp;
1751 if ((tmp & 0x10) == 0x10) {
1752 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1753 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1754 if ((tmp & 0x10) == 0x10)
1755 goto error;
1756 } else {
1757 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1758 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1759 if ((tmp & 0x10) != 0x10)
1760 goto error;
1761 }
1762 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1763 }
1764#endif
1765
1766 /*
1767 * Try to detect the chipset and its mode.
1768 */
1769 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1770 goto error;
1771
1772 return (0);
1773
1774error:
1775#if defined(__i386__) && defined(PC98)
1776 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1777 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1778 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1779 }
1780#endif
1781 if (ppc->res_irq != 0) {
1782 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1783 ppc->res_irq);
1784 }
1785 if (ppc->res_ioport != 0) {
1786 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1787 ppc->res_ioport);
1788 }
1789 if (ppc->res_drq != 0) {
1790 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1791 ppc->res_drq);
1792 }
1793 return (ENXIO);
1794}
1795
1796int
1797ppc_attach(device_t dev)
1798{
1799 struct ppc_data *ppc = DEVTOSOFTC(dev);
1800 device_t ppbus;
1801 int error;
1802
1803 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1804 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1805 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1806 ppc_epp_protocol[ppc->ppc_epp] : "");
| 1683 }
1684#endif /* PC98 */
1685 bus_set_resource(dev, SYS_RES_IOPORT, rid, port,
1686 IO_LPTSIZE_EXTENDED);
1687 }
1688#endif
1689
1690 /* IO port is mandatory */
1691
1692 /* Try "extended" IO port range...*/
1693 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1694 &ppc->rid_ioport, 0, ~0,
1695 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1696
1697 if (ppc->res_ioport != 0) {
1698 if (bootverbose)
1699 device_printf(dev, "using extended I/O port range\n");
1700 } else {
1701 /* Failed? If so, then try the "normal" IO port range... */
1702 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1703 &ppc->rid_ioport, 0, ~0,
1704 IO_LPTSIZE_NORMAL,
1705 RF_ACTIVE);
1706 if (ppc->res_ioport != 0) {
1707 if (bootverbose)
1708 device_printf(dev, "using normal I/O port range\n");
1709 } else {
1710 device_printf(dev, "cannot reserve I/O port range\n");
1711 goto error;
1712 }
1713 }
1714
1715 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1716
1717 ppc->ppc_flags = device_get_flags(dev);
1718
1719 if (!(ppc->ppc_flags & 0x20)) {
1720 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1721 &ppc->rid_irq,
1722 RF_SHAREABLE);
1723 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ,
1724 &ppc->rid_drq,
1725 RF_ACTIVE);
1726 }
1727
1728 if (ppc->res_irq)
1729 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1730 if (ppc->res_drq)
1731 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1732
1733 ppc->ppc_dev = dev;
1734 ppc->ppc_model = GENERIC;
1735
1736 ppc->ppc_mode = PPB_COMPATIBLE;
1737 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1738
1739 ppc->ppc_type = PPC_TYPE_GENERIC;
1740
1741#if defined(__i386__) && defined(PC98)
1742 /*
1743 * IEEE STD 1284 Function Check and Enable
1744 * for default IEEE-1284 port of NEC PC-98x1
1745 */
1746 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1747 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1748 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1749 pc98_ieee_mode = tmp;
1750 if ((tmp & 0x10) == 0x10) {
1751 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp & ~0x10);
1752 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1753 if ((tmp & 0x10) == 0x10)
1754 goto error;
1755 } else {
1756 outb(ppc->ppc_base + PPC_1284_ENABLE, tmp | 0x10);
1757 tmp = inb(ppc->ppc_base + PPC_1284_ENABLE);
1758 if ((tmp & 0x10) != 0x10)
1759 goto error;
1760 }
1761 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode | 0x10);
1762 }
1763#endif
1764
1765 /*
1766 * Try to detect the chipset and its mode.
1767 */
1768 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1769 goto error;
1770
1771 return (0);
1772
1773error:
1774#if defined(__i386__) && defined(PC98)
1775 if (ppc->ppc_base == PC98_IEEE_1284_PORT &&
1776 !(ppc->ppc_flags & PC98_IEEE_1284_DISABLE)) {
1777 outb(ppc->ppc_base + PPC_1284_ENABLE, pc98_ieee_mode);
1778 }
1779#endif
1780 if (ppc->res_irq != 0) {
1781 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1782 ppc->res_irq);
1783 }
1784 if (ppc->res_ioport != 0) {
1785 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1786 ppc->res_ioport);
1787 }
1788 if (ppc->res_drq != 0) {
1789 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1790 ppc->res_drq);
1791 }
1792 return (ENXIO);
1793}
1794
1795int
1796ppc_attach(device_t dev)
1797{
1798 struct ppc_data *ppc = DEVTOSOFTC(dev);
1799 device_t ppbus;
1800 int error;
1801
1802 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1803 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1804 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1805 ppc_epp_protocol[ppc->ppc_epp] : "");
|
1807
| 1806
|
1808 if (ppc->ppc_fifo)
1809 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1810 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1811
1812 if (ppc->res_irq) {
1813 /*
1814 * Create an interrupt event to manage the handlers of
1815 * child devices.
1816 */
1817 error = intr_event_create(&ppc->ppc_intr_event, ppc, 0, -1,
1818 NULL, NULL, NULL, NULL, "%s:", device_get_nameunit(dev));
1819 if (error) {
1820 device_printf(dev,
1821 "failed to create interrupt event: %d\n", error);
1822 return (error);
1823 }
1824
1825 /* default to the tty mask for registration */ /* XXX */
1826 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY,
1827 NULL, ppcintr, ppc, &ppc->intr_cookie);
1828 if (error) {
1829 device_printf(dev,
1830 "failed to register interrupt handler: %d\n",
1831 error);
1832 return (error);
1833 }
1834 }
1835
1836 /* add ppbus as a child of this isa to parallel bridge */
1837 ppbus = device_add_child(dev, "ppbus", -1);
1838
1839 /*
1840 * Probe the ppbus and attach devices found.
1841 */
1842 device_probe_and_attach(ppbus);
1843
1844 return (0);
1845}
1846
1847int
1848ppc_detach(device_t dev)
1849{
1850 struct ppc_data *ppc = DEVTOSOFTC(dev);
1851 device_t *children;
1852 int nchildren, i;
1853
1854 if (ppc->res_irq == 0) {
1855 return (ENXIO);
1856 }
1857
1858 /* detach & delete all children */
1859 if (!device_get_children(dev, &children, &nchildren)) {
1860 for (i = 0; i < nchildren; i++)
1861 if (children[i])
1862 device_delete_child(dev, children[i]);
1863 free(children, M_TEMP);
1864 }
1865
1866 if (ppc->res_irq != 0) {
1867 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1868 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1869 ppc->res_irq);
1870 }
1871 if (ppc->res_ioport != 0) {
1872 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1873 ppc->res_ioport);
1874 }
1875 if (ppc->res_drq != 0) {
1876 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1877 ppc->res_drq);
1878 }
1879
1880 return (0);
1881}
1882
1883u_char
1884ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1885{
1886 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
| 1807 if (ppc->ppc_fifo)
1808 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1809 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1810
1811 if (ppc->res_irq) {
1812 /*
1813 * Create an interrupt event to manage the handlers of
1814 * child devices.
1815 */
1816 error = intr_event_create(&ppc->ppc_intr_event, ppc, 0, -1,
1817 NULL, NULL, NULL, NULL, "%s:", device_get_nameunit(dev));
1818 if (error) {
1819 device_printf(dev,
1820 "failed to create interrupt event: %d\n", error);
1821 return (error);
1822 }
1823
1824 /* default to the tty mask for registration */ /* XXX */
1825 error = bus_setup_intr(dev, ppc->res_irq, INTR_TYPE_TTY,
1826 NULL, ppcintr, ppc, &ppc->intr_cookie);
1827 if (error) {
1828 device_printf(dev,
1829 "failed to register interrupt handler: %d\n",
1830 error);
1831 return (error);
1832 }
1833 }
1834
1835 /* add ppbus as a child of this isa to parallel bridge */
1836 ppbus = device_add_child(dev, "ppbus", -1);
1837
1838 /*
1839 * Probe the ppbus and attach devices found.
1840 */
1841 device_probe_and_attach(ppbus);
1842
1843 return (0);
1844}
1845
1846int
1847ppc_detach(device_t dev)
1848{
1849 struct ppc_data *ppc = DEVTOSOFTC(dev);
1850 device_t *children;
1851 int nchildren, i;
1852
1853 if (ppc->res_irq == 0) {
1854 return (ENXIO);
1855 }
1856
1857 /* detach & delete all children */
1858 if (!device_get_children(dev, &children, &nchildren)) {
1859 for (i = 0; i < nchildren; i++)
1860 if (children[i])
1861 device_delete_child(dev, children[i]);
1862 free(children, M_TEMP);
1863 }
1864
1865 if (ppc->res_irq != 0) {
1866 bus_teardown_intr(dev, ppc->res_irq, ppc->intr_cookie);
1867 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1868 ppc->res_irq);
1869 }
1870 if (ppc->res_ioport != 0) {
1871 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1872 ppc->res_ioport);
1873 }
1874 if (ppc->res_drq != 0) {
1875 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1876 ppc->res_drq);
1877 }
1878
1879 return (0);
1880}
1881
1882u_char
1883ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
1884{
1885 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
|
| 1886
|
1887 switch (iop) {
1888 case PPB_OUTSB_EPP:
1889 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1890 break;
1891 case PPB_OUTSW_EPP:
1892 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1893 break;
1894 case PPB_OUTSL_EPP:
1895 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1896 break;
1897 case PPB_INSB_EPP:
1898 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1899 break;
1900 case PPB_INSW_EPP:
1901 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1902 break;
1903 case PPB_INSL_EPP:
1904 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1905 break;
1906 case PPB_RDTR:
1907 return (r_dtr(ppc));
1908 case PPB_RSTR:
1909 return (r_str(ppc));
1910 case PPB_RCTR:
1911 return (r_ctr(ppc));
1912 case PPB_REPP_A:
1913 return (r_epp_A(ppc));
1914 case PPB_REPP_D:
1915 return (r_epp_D(ppc));
1916 case PPB_RECR:
1917 return (r_ecr(ppc));
1918 case PPB_RFIFO:
1919 return (r_fifo(ppc));
1920 case PPB_WDTR:
1921 w_dtr(ppc, byte);
1922 break;
1923 case PPB_WSTR:
1924 w_str(ppc, byte);
1925 break;
1926 case PPB_WCTR:
1927 w_ctr(ppc, byte);
1928 break;
1929 case PPB_WEPP_A:
1930 w_epp_A(ppc, byte);
1931 break;
1932 case PPB_WEPP_D:
1933 w_epp_D(ppc, byte);
1934 break;
1935 case PPB_WECR:
1936 w_ecr(ppc, byte);
1937 break;
1938 case PPB_WFIFO:
1939 w_fifo(ppc, byte);
1940 break;
1941 default:
1942 panic("%s: unknown I/O operation", __func__);
1943 break;
1944 }
1945
1946 return (0); /* not significative */
1947}
1948
1949int
1950ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1951{
1952 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1953
1954 switch (index) {
1955 case PPC_IVAR_EPP_PROTO:
1956 *val = (u_long)ppc->ppc_epp;
1957 break;
1958 default:
1959 return (ENOENT);
1960 }
1961
1962 return (0);
1963}
1964
1965/*
1966 * We allow child devices to allocate an IRQ resource at rid 0 for their
1967 * interrupt handlers.
1968 */
1969struct resource *
1970ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1971 u_long start, u_long end, u_long count, u_int flags)
1972{
1973 struct ppc_data *ppc = DEVTOSOFTC(bus);
1974
1975 switch (type) {
1976 case SYS_RES_IRQ:
1977 if (*rid == 0)
1978 return (ppc->res_irq);
1979 break;
1980 }
1981 return (NULL);
1982}
1983
1984int
1985ppc_release_resource(device_t bus, device_t child, int type, int rid,
1986 struct resource *r)
1987{
1988#ifdef INVARIANTS
1989 struct ppc_data *ppc = DEVTOSOFTC(bus);
1990#endif
1991
1992 switch (type) {
1993 case SYS_RES_IRQ:
1994 if (rid == 0) {
1995 KASSERT(r == ppc->res_irq,
1996 ("ppc child IRQ resource mismatch"));
1997 return (0);
1998 }
1999 break;
2000 }
2001 return (EINVAL);
2002}
2003
2004/*
2005 * If a child wants to add a handler for our IRQ, add it to our interrupt
2006 * event. Otherwise, fail the request.
2007 */
2008int
2009ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2010 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep)
2011{
2012 struct ppc_data *ppc = DEVTOSOFTC(bus);
2013 int error;
2014
2015 if (r != ppc->res_irq)
2016 return (EINVAL);
2017
2018 /* We don't allow filters. */
2019 if (filt != NULL)
2020 return (EINVAL);
2021
2022 error = intr_event_add_handler(ppc->ppc_intr_event,
2023 device_get_nameunit(child), NULL, ihand, arg, intr_priority(flags),
2024 flags, cookiep);
2025 if (error == 0)
2026 ppc->ppc_child_handlers++;
2027 return (error);
2028}
2029
2030int
2031ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *cookie)
2032{
2033 struct ppc_data *ppc = DEVTOSOFTC(bus);
2034 int error;
2035
2036 if (r != ppc->res_irq)
2037 return (EINVAL);
2038
2039 KASSERT(intr_handler_source(cookie) == ppc,
2040 ("ppc_teardown_intr: source mismatch"));
2041 error = intr_event_remove_handler(cookie);
2042 if (error == 0)
2043 ppc->ppc_child_handlers--;
2044 return (error);
2045}
2046
2047MODULE_DEPEND(ppc, ppbus, 1, 1, 1);
| 1887 switch (iop) {
1888 case PPB_OUTSB_EPP:
1889 bus_write_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1890 break;
1891 case PPB_OUTSW_EPP:
1892 bus_write_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1893 break;
1894 case PPB_OUTSL_EPP:
1895 bus_write_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1896 break;
1897 case PPB_INSB_EPP:
1898 bus_read_multi_1(ppc->res_ioport, PPC_EPP_DATA, addr, cnt);
1899 break;
1900 case PPB_INSW_EPP:
1901 bus_read_multi_2(ppc->res_ioport, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
1902 break;
1903 case PPB_INSL_EPP:
1904 bus_read_multi_4(ppc->res_ioport, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
1905 break;
1906 case PPB_RDTR:
1907 return (r_dtr(ppc));
1908 case PPB_RSTR:
1909 return (r_str(ppc));
1910 case PPB_RCTR:
1911 return (r_ctr(ppc));
1912 case PPB_REPP_A:
1913 return (r_epp_A(ppc));
1914 case PPB_REPP_D:
1915 return (r_epp_D(ppc));
1916 case PPB_RECR:
1917 return (r_ecr(ppc));
1918 case PPB_RFIFO:
1919 return (r_fifo(ppc));
1920 case PPB_WDTR:
1921 w_dtr(ppc, byte);
1922 break;
1923 case PPB_WSTR:
1924 w_str(ppc, byte);
1925 break;
1926 case PPB_WCTR:
1927 w_ctr(ppc, byte);
1928 break;
1929 case PPB_WEPP_A:
1930 w_epp_A(ppc, byte);
1931 break;
1932 case PPB_WEPP_D:
1933 w_epp_D(ppc, byte);
1934 break;
1935 case PPB_WECR:
1936 w_ecr(ppc, byte);
1937 break;
1938 case PPB_WFIFO:
1939 w_fifo(ppc, byte);
1940 break;
1941 default:
1942 panic("%s: unknown I/O operation", __func__);
1943 break;
1944 }
1945
1946 return (0); /* not significative */
1947}
1948
1949int
1950ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
1951{
1952 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
1953
1954 switch (index) {
1955 case PPC_IVAR_EPP_PROTO:
1956 *val = (u_long)ppc->ppc_epp;
1957 break;
1958 default:
1959 return (ENOENT);
1960 }
1961
1962 return (0);
1963}
1964
1965/*
1966 * We allow child devices to allocate an IRQ resource at rid 0 for their
1967 * interrupt handlers.
1968 */
1969struct resource *
1970ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
1971 u_long start, u_long end, u_long count, u_int flags)
1972{
1973 struct ppc_data *ppc = DEVTOSOFTC(bus);
1974
1975 switch (type) {
1976 case SYS_RES_IRQ:
1977 if (*rid == 0)
1978 return (ppc->res_irq);
1979 break;
1980 }
1981 return (NULL);
1982}
1983
1984int
1985ppc_release_resource(device_t bus, device_t child, int type, int rid,
1986 struct resource *r)
1987{
1988#ifdef INVARIANTS
1989 struct ppc_data *ppc = DEVTOSOFTC(bus);
1990#endif
1991
1992 switch (type) {
1993 case SYS_RES_IRQ:
1994 if (rid == 0) {
1995 KASSERT(r == ppc->res_irq,
1996 ("ppc child IRQ resource mismatch"));
1997 return (0);
1998 }
1999 break;
2000 }
2001 return (EINVAL);
2002}
2003
2004/*
2005 * If a child wants to add a handler for our IRQ, add it to our interrupt
2006 * event. Otherwise, fail the request.
2007 */
2008int
2009ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2010 driver_filter_t *filt, void (*ihand)(void *), void *arg, void **cookiep)
2011{
2012 struct ppc_data *ppc = DEVTOSOFTC(bus);
2013 int error;
2014
2015 if (r != ppc->res_irq)
2016 return (EINVAL);
2017
2018 /* We don't allow filters. */
2019 if (filt != NULL)
2020 return (EINVAL);
2021
2022 error = intr_event_add_handler(ppc->ppc_intr_event,
2023 device_get_nameunit(child), NULL, ihand, arg, intr_priority(flags),
2024 flags, cookiep);
2025 if (error == 0)
2026 ppc->ppc_child_handlers++;
2027 return (error);
2028}
2029
2030int
2031ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *cookie)
2032{
2033 struct ppc_data *ppc = DEVTOSOFTC(bus);
2034 int error;
2035
2036 if (r != ppc->res_irq)
2037 return (EINVAL);
2038
2039 KASSERT(intr_handler_source(cookie) == ppc,
2040 ("ppc_teardown_intr: source mismatch"));
2041 error = intr_event_remove_handler(cookie);
2042 if (error == 0)
2043 ppc->ppc_child_handlers--;
2044 return (error);
2045}
2046
2047MODULE_DEPEND(ppc, ppbus, 1, 1, 1);
|