1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 122678 2003-11-14 17:16:58Z obrien $");
36
37/*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
55 *
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
60 * hardware support.
61 *
62 * Special thanks to:
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
70 */
71
72#include <sys/param.h>
73#include <sys/systm.h>
74#include <sys/sockio.h>
75#include <sys/mbuf.h>
76#include <sys/malloc.h>
77#include <sys/kernel.h>
78#include <sys/socket.h>
79
80#include <net/if.h>
81#include <net/if_arp.h>
82#include <net/ethernet.h>
83#include <net/if_dl.h>
84#include <net/if_media.h>
85
86#include <net/bpf.h>
87
88#include <vm/vm.h> /* for vtophys */
89#include <vm/pmap.h> /* for vtophys */
90#include <machine/clock.h> /* for DELAY */
91#include <machine/bus_pio.h>
92#include <machine/bus_memio.h>
93#include <machine/bus.h>
94#include <machine/resource.h>
95#include <sys/bus.h>
96#include <sys/rman.h>
97
98#include <dev/mii/mii.h>
99#include <dev/mii/miivar.h>
100
101#include <dev/pci/pcireg.h>
102#include <dev/pci/pcivar.h>
103
104#define LGE_USEIOSPACE
105
106#include <dev/lge/if_lgereg.h>
107
108/* "controller miibus0" required. See GENERIC if you get errors here. */
109#include "miibus_if.h"
110
111/*
112 * Various supported device vendors/types and their names.
113 */
114static struct lge_type lge_devs[] = {
115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
116 { 0, 0, NULL }
117};
118
119static int lge_probe(device_t);
120static int lge_attach(device_t);
121static int lge_detach(device_t);
122
123static int lge_alloc_jumbo_mem(struct lge_softc *);
124static void lge_free_jumbo_mem(struct lge_softc *);
125static void *lge_jalloc(struct lge_softc *);
126static void lge_jfree(void *, void *);
127
128static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130static void lge_rxeof(struct lge_softc *, int);
131static void lge_rxeoc(struct lge_softc *);
132static void lge_txeof(struct lge_softc *);
133static void lge_intr(void *);
134static void lge_tick(void *);
135static void lge_start(struct ifnet *);
136static int lge_ioctl(struct ifnet *, u_long, caddr_t);
137static void lge_init(void *);
138static void lge_stop(struct lge_softc *);
139static void lge_watchdog(struct ifnet *);
140static void lge_shutdown(device_t);
141static int lge_ifmedia_upd(struct ifnet *);
142static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
143
144static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
145static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
146
147static int lge_miibus_readreg(device_t, int, int);
148static int lge_miibus_writereg(device_t, int, int, int);
149static void lge_miibus_statchg(device_t);
150
151static void lge_setmulti(struct lge_softc *);
152static u_int32_t lge_mchash(caddr_t);
153static void lge_reset(struct lge_softc *);
154static int lge_list_rx_init(struct lge_softc *);
155static int lge_list_tx_init(struct lge_softc *);
156
157#ifdef LGE_USEIOSPACE
158#define LGE_RES SYS_RES_IOPORT
159#define LGE_RID LGE_PCI_LOIO
160#else
161#define LGE_RES SYS_RES_MEMORY
162#define LGE_RID LGE_PCI_LOMEM
163#endif
164
165static device_method_t lge_methods[] = {
166 /* Device interface */
167 DEVMETHOD(device_probe, lge_probe),
168 DEVMETHOD(device_attach, lge_attach),
169 DEVMETHOD(device_detach, lge_detach),
170 DEVMETHOD(device_shutdown, lge_shutdown),
171
172 /* bus interface */
173 DEVMETHOD(bus_print_child, bus_generic_print_child),
174 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
175
176 /* MII interface */
177 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
178 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
179 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
180
181 { 0, 0 }
182};
183
184static driver_t lge_driver = {
185 "lge",
186 lge_methods,
187 sizeof(struct lge_softc)
188};
189
190static devclass_t lge_devclass;
191
192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
194MODULE_DEPEND(lge, pci, 1, 1, 1);
195MODULE_DEPEND(lge, ether, 1, 1, 1);
196MODULE_DEPEND(lge, miibus, 1, 1, 1);
197
198#define LGE_SETBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) | (x))
201
202#define LGE_CLRBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, \
204 CSR_READ_4(sc, reg) & ~(x))
205
206#define SIO_SET(x) \
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208
209#define SIO_CLR(x) \
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
211
212/*
213 * Read a word of data stored in the EEPROM at address 'addr.'
214 */
215static void
216lge_eeprom_getword(sc, addr, dest)
217 struct lge_softc *sc;
218 int addr;
219 u_int16_t *dest;
220{
221 register int i;
222 u_int32_t val;
223
224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
226
227 for (i = 0; i < LGE_TIMEOUT; i++)
228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
229 break;
230
231 if (i == LGE_TIMEOUT) {
232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
233 return;
234 }
235
236 val = CSR_READ_4(sc, LGE_EEDATA);
237
238 if (addr & 1)
239 *dest = (val >> 16) & 0xFFFF;
240 else
241 *dest = val & 0xFFFF;
242
243 return;
244}
245
246/*
247 * Read a sequence of words from the EEPROM.
248 */
249static void
250lge_read_eeprom(sc, dest, off, cnt, swap)
251 struct lge_softc *sc;
252 caddr_t dest;
253 int off;
254 int cnt;
255 int swap;
256{
257 int i;
258 u_int16_t word = 0, *ptr;
259
260 for (i = 0; i < cnt; i++) {
261 lge_eeprom_getword(sc, off + i, &word);
262 ptr = (u_int16_t *)(dest + (i * 2));
263 if (swap)
264 *ptr = ntohs(word);
265 else
266 *ptr = word;
267 }
268
269 return;
270}
271
272static int
273lge_miibus_readreg(dev, phy, reg)
274 device_t dev;
275 int phy, reg;
276{
277 struct lge_softc *sc;
278 int i;
279
280 sc = device_get_softc(dev);
281
282 /*
283 * If we have a non-PCS PHY, pretend that the internal
284 * autoneg stuff at PHY address 0 isn't there so that
285 * the miibus code will find only the GMII PHY.
286 */
287 if (sc->lge_pcs == 0 && phy == 0)
288 return(0);
289
290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
291
292 for (i = 0; i < LGE_TIMEOUT; i++)
293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
294 break;
295
296 if (i == LGE_TIMEOUT) {
297 printf("lge%d: PHY read timed out\n", sc->lge_unit);
298 return(0);
299 }
300
301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
302}
303
304static int
305lge_miibus_writereg(dev, phy, reg, data)
306 device_t dev;
307 int phy, reg, data;
308{
309 struct lge_softc *sc;
310 int i;
311
312 sc = device_get_softc(dev);
313
314 CSR_WRITE_4(sc, LGE_GMIICTL,
315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
316
317 for (i = 0; i < LGE_TIMEOUT; i++)
318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
319 break;
320
321 if (i == LGE_TIMEOUT) {
322 printf("lge%d: PHY write timed out\n", sc->lge_unit);
323 return(0);
324 }
325
326 return(0);
327}
328
329static void
330lge_miibus_statchg(dev)
331 device_t dev;
332{
333 struct lge_softc *sc;
334 struct mii_data *mii;
335
336 sc = device_get_softc(dev);
337 mii = device_get_softc(sc->lge_miibus);
338
339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
340 switch (IFM_SUBTYPE(mii->mii_media_active)) {
341 case IFM_1000_T:
342 case IFM_1000_SX:
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
344 break;
345 case IFM_100_TX:
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
347 break;
348 case IFM_10_T:
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
350 break;
351 default:
352 /*
353 * Choose something, even if it's wrong. Clearing
354 * all the bits will hose autoneg on the internal
355 * PHY.
356 */
357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
358 break;
359 }
360
361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
363 } else {
364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
365 }
366
367 return;
368}
369
370static u_int32_t
371lge_mchash(addr)
372 caddr_t addr;
373{
374 u_int32_t crc, carry;
375 int idx, bit;
376 u_int8_t data;
377
378 /* Compute CRC for the address value. */
379 crc = 0xFFFFFFFF; /* initial value */
380
381 for (idx = 0; idx < 6; idx++) {
382 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
383 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
384 crc <<= 1;
385 if (carry)
386 crc = (crc ^ 0x04c11db6) | carry;
387 }
388 }
389
390 /*
391 * return the filter bit position
392 */
393 return((crc >> 26) & 0x0000003F);
394}
395
396static void
397lge_setmulti(sc)
398 struct lge_softc *sc;
399{
400 struct ifnet *ifp;
401 struct ifmultiaddr *ifma;
402 u_int32_t h = 0, hashes[2] = { 0, 0 };
403
404 ifp = &sc->arpcom.ac_if;
405
406 /* Make sure multicast hash table is enabled. */
407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
408
409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
412 return;
413 }
414
415 /* first, zot all the existing hash bits */
416 CSR_WRITE_4(sc, LGE_MAR0, 0);
417 CSR_WRITE_4(sc, LGE_MAR1, 0);
418
419 /* now program new ones */
420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
421 if (ifma->ifma_addr->sa_family != AF_LINK)
422 continue;
423 h = lge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
424 if (h < 32)
425 hashes[0] |= (1 << h);
426 else
427 hashes[1] |= (1 << (h - 32));
428 }
429
430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
432
433 return;
434}
435
436static void
437lge_reset(sc)
438 struct lge_softc *sc;
439{
440 register int i;
441
442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
443
444 for (i = 0; i < LGE_TIMEOUT; i++) {
445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
446 break;
447 }
448
449 if (i == LGE_TIMEOUT)
450 printf("lge%d: reset never completed\n", sc->lge_unit);
451
452 /* Wait a little while for the chip to get its brains in order. */
453 DELAY(1000);
454
455 return;
456}
457
458/*
459 * Probe for a Level 1 chip. Check the PCI vendor and device
460 * IDs against our list and return a device name if we find a match.
461 */
462static int
463lge_probe(dev)
464 device_t dev;
465{
466 struct lge_type *t;
467
468 t = lge_devs;
469
470 while(t->lge_name != NULL) {
471 if ((pci_get_vendor(dev) == t->lge_vid) &&
472 (pci_get_device(dev) == t->lge_did)) {
473 device_set_desc(dev, t->lge_name);
474 return(0);
475 }
476 t++;
477 }
478
479 return(ENXIO);
480}
481
482/*
483 * Attach the interface. Allocate softc structures, do ifmedia
484 * setup and ethernet/BPF attach.
485 */
486static int
487lge_attach(dev)
488 device_t dev;
489{
490 int s;
491 u_char eaddr[ETHER_ADDR_LEN];
492 struct lge_softc *sc;
493 struct ifnet *ifp;
494 int unit, error = 0, rid;
495
496 s = splimp();
497
498 sc = device_get_softc(dev);
499 unit = device_get_unit(dev);
500 bzero(sc, sizeof(struct lge_softc));
501#ifndef BURN_BRIDGES
502 /*
503 * Handle power management nonsense.
504 */
505 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
506 u_int32_t iobase, membase, irq;
507
508 /* Save important PCI config data. */
509 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
510 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
511 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
512
513 /* Reset the power state. */
514 printf("lge%d: chip is in D%d power mode "
515 "-- setting to D0\n", unit,
516 pci_get_powerstate(dev));
517 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
518
519 /* Restore PCI config data. */
520 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
521 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
522 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
523 }
524#endif
525 /*
526 * Map control/status registers.
527 */
528 pci_enable_busmaster(dev);
529
530 rid = LGE_RID;
531 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
532 0, ~0, 1, RF_ACTIVE);
533
534 if (sc->lge_res == NULL) {
535 printf("lge%d: couldn't map ports/memory\n", unit);
536 error = ENXIO;
537 goto fail;
538 }
539
540 sc->lge_btag = rman_get_bustag(sc->lge_res);
541 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
542
543 /* Allocate interrupt */
544 rid = 0;
545 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
546 RF_SHAREABLE | RF_ACTIVE);
547
548 if (sc->lge_irq == NULL) {
549 printf("lge%d: couldn't map interrupt\n", unit);
550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
551 error = ENXIO;
552 goto fail;
553 }
554
555 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
556 lge_intr, sc, &sc->lge_intrhand);
557
558 if (error) {
559 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
560 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
561 printf("lge%d: couldn't set up irq\n", unit);
562 goto fail;
563 }
564
565 /* Reset the adapter. */
566 lge_reset(sc);
567
568 /*
569 * Get station address from the EEPROM.
570 */
571 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
572 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
573 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
574
575 /*
576 * A Level 1 chip was detected. Inform the world.
577 */
578 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
579
580 sc->lge_unit = unit;
581 callout_handle_init(&sc->lge_stat_ch);
582 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
583
584 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
585 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
586
587 if (sc->lge_ldata == NULL) {
588 printf("lge%d: no memory for list buffers!\n", unit);
589 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
592 error = ENXIO;
593 goto fail;
594 }
595 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
596
597 /* Try to allocate memory for jumbo buffers. */
598 if (lge_alloc_jumbo_mem(sc)) {
599 printf("lge%d: jumbo buffer allocation failed\n",
600 sc->lge_unit);
601 contigfree(sc->lge_ldata,
602 sizeof(struct lge_list_data), M_DEVBUF);
603 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
605 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
606 error = ENXIO;
607 goto fail;
608 }
609
610 ifp = &sc->arpcom.ac_if;
611 ifp->if_softc = sc;
612 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
613 ifp->if_mtu = ETHERMTU;
614 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
615 ifp->if_ioctl = lge_ioctl;
616 ifp->if_output = ether_output;
617 ifp->if_start = lge_start;
618 ifp->if_watchdog = lge_watchdog;
619 ifp->if_init = lge_init;
620 ifp->if_baudrate = 1000000000;
621 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
622 ifp->if_capabilities = IFCAP_RXCSUM;
623 ifp->if_capenable = ifp->if_capabilities;
624
625 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
626 sc->lge_pcs = 1;
627 else
628 sc->lge_pcs = 0;
629
630 /*
631 * Do MII setup.
632 */
633 if (mii_phy_probe(dev, &sc->lge_miibus,
634 lge_ifmedia_upd, lge_ifmedia_sts)) {
635 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
636 contigfree(sc->lge_ldata,
637 sizeof(struct lge_list_data), M_DEVBUF);
638 lge_free_jumbo_mem(sc);
639 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
640 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
641 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
642 error = ENXIO;
643 goto fail;
644 }
645
646 /*
647 * Call MI attach routine.
648 */
649 ether_ifattach(ifp, eaddr);
650 callout_handle_init(&sc->lge_stat_ch);
651
652fail:
653 splx(s);
654 return(error);
655}
656
657static int
658lge_detach(dev)
659 device_t dev;
660{
661 struct lge_softc *sc;
662 struct ifnet *ifp;
663 int s;
664
665 s = splimp();
666
667 sc = device_get_softc(dev);
668 ifp = &sc->arpcom.ac_if;
669
670 lge_reset(sc);
671 lge_stop(sc);
672 ether_ifdetach(ifp);
673
674 bus_generic_detach(dev);
675 device_delete_child(dev, sc->lge_miibus);
676
677 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
679 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
680
681 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
682 lge_free_jumbo_mem(sc);
683
684 splx(s);
685
686 return(0);
687}
688
689/*
690 * Initialize the transmit descriptors.
691 */
692static int
693lge_list_tx_init(sc)
694 struct lge_softc *sc;
695{
696 struct lge_list_data *ld;
697 struct lge_ring_data *cd;
698 int i;
699
700 cd = &sc->lge_cdata;
701 ld = sc->lge_ldata;
702 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
703 ld->lge_tx_list[i].lge_mbuf = NULL;
704 ld->lge_tx_list[i].lge_ctl = 0;
705 }
706
707 cd->lge_tx_prod = cd->lge_tx_cons = 0;
708
709 return(0);
710}
711
712
713/*
714 * Initialize the RX descriptors and allocate mbufs for them. Note that
715 * we arralge the descriptors in a closed ring, so that the last descriptor
716 * points back to the first.
717 */
718static int
719lge_list_rx_init(sc)
720 struct lge_softc *sc;
721{
722 struct lge_list_data *ld;
723 struct lge_ring_data *cd;
724 int i;
725
726 ld = sc->lge_ldata;
727 cd = &sc->lge_cdata;
728
729 cd->lge_rx_prod = cd->lge_rx_cons = 0;
730
731 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
732
733 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
734 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
735 break;
736 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
737 return(ENOBUFS);
738 }
739
740 /* Clear possible 'rx command queue empty' interrupt. */
741 CSR_READ_4(sc, LGE_ISR);
742
743 return(0);
744}
745
746/*
747 * Initialize an RX descriptor and attach an MBUF cluster.
748 */
749static int
750lge_newbuf(sc, c, m)
751 struct lge_softc *sc;
752 struct lge_rx_desc *c;
753 struct mbuf *m;
754{
755 struct mbuf *m_new = NULL;
756 caddr_t *buf = NULL;
757
758 if (m == NULL) {
759 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
760 if (m_new == NULL) {
761 printf("lge%d: no memory for rx list "
762 "-- packet dropped!\n", sc->lge_unit);
763 return(ENOBUFS);
764 }
765
766 /* Allocate the jumbo buffer */
767 buf = lge_jalloc(sc);
768 if (buf == NULL) {
769#ifdef LGE_VERBOSE
770 printf("lge%d: jumbo allocation failed "
771 "-- packet dropped!\n", sc->lge_unit);
772#endif
773 m_freem(m_new);
774 return(ENOBUFS);
775 }
776 /* Attach the buffer to the mbuf */
777 m_new->m_data = (void *)buf;
778 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
779 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
780 (struct lge_softc *)sc, 0, EXT_NET_DRV);
781 } else {
782 m_new = m;
783 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
784 m_new->m_data = m_new->m_ext.ext_buf;
785 }
786
787 /*
788 * Adjust alignment so packet payload begins on a
789 * longword boundary. Mandatory for Alpha, useful on
790 * x86 too.
791 */
792 m_adj(m_new, ETHER_ALIGN);
793
794 c->lge_mbuf = m_new;
795 c->lge_fragptr_hi = 0;
796 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
797 c->lge_fraglen = m_new->m_len;
798 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
799 c->lge_sts = 0;
800
801 /*
802 * Put this buffer in the RX command FIFO. To do this,
803 * we just write the physical address of the descriptor
804 * into the RX descriptor address registers. Note that
805 * there are two registers, one high DWORD and one low
806 * DWORD, which lets us specify a 64-bit address if
807 * desired. We only use a 32-bit address for now.
808 * Writing to the low DWORD register is what actually
809 * causes the command to be issued, so we do that
810 * last.
811 */
812 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
813 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
814
815 return(0);
816}
817
818static int
819lge_alloc_jumbo_mem(sc)
820 struct lge_softc *sc;
821{
822 caddr_t ptr;
823 register int i;
824 struct lge_jpool_entry *entry;
825
826 /* Grab a big chunk o' storage. */
827 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
828 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
829
830 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
831 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
832 return(ENOBUFS);
833 }
834
835 SLIST_INIT(&sc->lge_jfree_listhead);
836 SLIST_INIT(&sc->lge_jinuse_listhead);
837
838 /*
839 * Now divide it up into 9K pieces and save the addresses
840 * in an array.
841 */
842 ptr = sc->lge_cdata.lge_jumbo_buf;
843 for (i = 0; i < LGE_JSLOTS; i++) {
844 sc->lge_cdata.lge_jslots[i] = ptr;
845 ptr += LGE_JLEN;
846 entry = malloc(sizeof(struct lge_jpool_entry),
847 M_DEVBUF, M_NOWAIT);
848 if (entry == NULL) {
849 printf("lge%d: no memory for jumbo "
850 "buffer queue!\n", sc->lge_unit);
851 return(ENOBUFS);
852 }
853 entry->slot = i;
854 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
855 entry, jpool_entries);
856 }
857
858 return(0);
859}
860
861static void
862lge_free_jumbo_mem(sc)
863 struct lge_softc *sc;
864{
865 int i;
866 struct lge_jpool_entry *entry;
867
868 for (i = 0; i < LGE_JSLOTS; i++) {
869 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
870 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
871 free(entry, M_DEVBUF);
872 }
873
874 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
875
876 return;
877}
878
879/*
880 * Allocate a jumbo buffer.
881 */
882static void *
883lge_jalloc(sc)
884 struct lge_softc *sc;
885{
886 struct lge_jpool_entry *entry;
887
888 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
889
890 if (entry == NULL) {
891#ifdef LGE_VERBOSE
892 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
893#endif
894 return(NULL);
895 }
896
897 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
898 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
899 return(sc->lge_cdata.lge_jslots[entry->slot]);
900}
901
902/*
903 * Release a jumbo buffer.
904 */
905static void
906lge_jfree(buf, args)
907 void *buf;
908 void *args;
909{
910 struct lge_softc *sc;
911 int i;
912 struct lge_jpool_entry *entry;
913
914 /* Extract the softc struct pointer. */
915 sc = args;
916
917 if (sc == NULL)
918 panic("lge_jfree: can't find softc pointer!");
919
920 /* calculate the slot this buffer belongs to */
921 i = ((vm_offset_t)buf
922 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
923
924 if ((i < 0) || (i >= LGE_JSLOTS))
925 panic("lge_jfree: asked to free buffer that we don't manage!");
926
927 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
928 if (entry == NULL)
929 panic("lge_jfree: buffer not in use!");
930 entry->slot = i;
931 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
932 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
933
934 return;
935}
936
937/*
938 * A frame has been uploaded: pass the resulting mbuf chain up to
939 * the higher level protocols.
940 */
941static void
942lge_rxeof(sc, cnt)
943 struct lge_softc *sc;
944 int cnt;
945{
946 struct mbuf *m;
947 struct ifnet *ifp;
948 struct lge_rx_desc *cur_rx;
949 int c, i, total_len = 0;
950 u_int32_t rxsts, rxctl;
951
952 ifp = &sc->arpcom.ac_if;
953
954 /* Find out how many frames were processed. */
955 c = cnt;
956 i = sc->lge_cdata.lge_rx_cons;
957
958 /* Suck them in. */
959 while(c) {
960 struct mbuf *m0 = NULL;
961
962 cur_rx = &sc->lge_ldata->lge_rx_list[i];
963 rxctl = cur_rx->lge_ctl;
964 rxsts = cur_rx->lge_sts;
965 m = cur_rx->lge_mbuf;
966 cur_rx->lge_mbuf = NULL;
967 total_len = LGE_RXBYTES(cur_rx);
968 LGE_INC(i, LGE_RX_LIST_CNT);
969 c--;
970
971 /*
972 * If an error occurs, update stats, clear the
973 * status word and leave the mbuf cluster in place:
974 * it should simply get re-used next time this descriptor
975 * comes up in the ring.
976 */
977 if (rxctl & LGE_RXCTL_ERRMASK) {
978 ifp->if_ierrors++;
979 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
980 continue;
981 }
982
983 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
984 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
985 ifp, NULL);
986 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
987 if (m0 == NULL) {
988 printf("lge%d: no receive buffers "
989 "available -- packet dropped!\n",
990 sc->lge_unit);
991 ifp->if_ierrors++;
992 continue;
993 }
994 m = m0;
995 } else {
996 m->m_pkthdr.rcvif = ifp;
997 m->m_pkthdr.len = m->m_len = total_len;
998 }
999
1000 ifp->if_ipackets++;
1001
1002 /* Do IP checksum checking. */
1003 if (rxsts & LGE_RXSTS_ISIP)
1004 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1005 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1006 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1007 if ((rxsts & LGE_RXSTS_ISTCP &&
1008 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1009 (rxsts & LGE_RXSTS_ISUDP &&
1010 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1011 m->m_pkthdr.csum_flags |=
1012 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1013 m->m_pkthdr.csum_data = 0xffff;
1014 }
1015
1016 (*ifp->if_input)(ifp, m);
1017 }
1018
1019 sc->lge_cdata.lge_rx_cons = i;
1020
1021 return;
1022}
1023
1024static void
1025lge_rxeoc(sc)
1026 struct lge_softc *sc;
1027{
1028 struct ifnet *ifp;
1029
1030 ifp = &sc->arpcom.ac_if;
1031 ifp->if_flags &= ~IFF_RUNNING;
1032 lge_init(sc);
1033 return;
1034}
1035
1036/*
1037 * A frame was downloaded to the chip. It's safe for us to clean up
1038 * the list buffers.
1039 */
1040
1041static void
1042lge_txeof(sc)
1043 struct lge_softc *sc;
1044{
1045 struct lge_tx_desc *cur_tx = NULL;
1046 struct ifnet *ifp;
1047 u_int32_t idx, txdone;
1048
1049 ifp = &sc->arpcom.ac_if;
1050
1051 /* Clear the timeout timer. */
1052 ifp->if_timer = 0;
1053
1054 /*
1055 * Go through our tx list and free mbufs for those
1056 * frames that have been transmitted.
1057 */
1058 idx = sc->lge_cdata.lge_tx_cons;
1059 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1060
1061 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1062 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1063
1064 ifp->if_opackets++;
1065 if (cur_tx->lge_mbuf != NULL) {
1066 m_freem(cur_tx->lge_mbuf);
1067 cur_tx->lge_mbuf = NULL;
1068 }
1069 cur_tx->lge_ctl = 0;
1070
1071 txdone--;
1072 LGE_INC(idx, LGE_TX_LIST_CNT);
1073 ifp->if_timer = 0;
1074 }
1075
1076 sc->lge_cdata.lge_tx_cons = idx;
1077
1078 if (cur_tx != NULL)
1079 ifp->if_flags &= ~IFF_OACTIVE;
1080
1081 return;
1082}
1083
1084static void
1085lge_tick(xsc)
1086 void *xsc;
1087{
1088 struct lge_softc *sc;
1089 struct mii_data *mii;
1090 struct ifnet *ifp;
1091 int s;
1092
1093 s = splimp();
1094
1095 sc = xsc;
1096 ifp = &sc->arpcom.ac_if;
1097
1098 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1099 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1100 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1101 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1102
1103 if (!sc->lge_link) {
1104 mii = device_get_softc(sc->lge_miibus);
1105 mii_tick(mii);
1106 if (mii->mii_media_status & IFM_ACTIVE &&
1107 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1108 sc->lge_link++;
1109 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1110 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1111 printf("lge%d: gigabit link up\n",
1112 sc->lge_unit);
1113 if (ifp->if_snd.ifq_head != NULL)
1114 lge_start(ifp);
1115 }
1116 }
1117
1118 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1119
1120 splx(s);
1121
1122 return;
1123}
1124
1125static void
1126lge_intr(arg)
1127 void *arg;
1128{
1129 struct lge_softc *sc;
1130 struct ifnet *ifp;
1131 u_int32_t status;
1132
1133 sc = arg;
1134 ifp = &sc->arpcom.ac_if;
1135
1136 /* Supress unwanted interrupts */
1137 if (!(ifp->if_flags & IFF_UP)) {
1138 lge_stop(sc);
1139 return;
1140 }
1141
1142 for (;;) {
1143 /*
1144 * Reading the ISR register clears all interrupts, and
1145 * clears the 'interrupts enabled' bit in the IMR
1146 * register.
1147 */
1148 status = CSR_READ_4(sc, LGE_ISR);
1149
1150 if ((status & LGE_INTRS) == 0)
1151 break;
1152
1153 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1154 lge_txeof(sc);
1155
1156 if (status & LGE_ISR_RXDMA_DONE)
1157 lge_rxeof(sc, LGE_RX_DMACNT(status));
1158
1159 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1160 lge_rxeoc(sc);
1161
1162 if (status & LGE_ISR_PHY_INTR) {
1163 sc->lge_link = 0;
1164 untimeout(lge_tick, sc, sc->lge_stat_ch);
1165 lge_tick(sc);
1166 }
1167 }
1168
1169 /* Re-enable interrupts. */
1170 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1171
1172 if (ifp->if_snd.ifq_head != NULL)
1173 lge_start(ifp);
1174
1175 return;
1176}
1177
1178/*
1179 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1180 * pointers to the fragment pointers.
1181 */
1182static int
1183lge_encap(sc, m_head, txidx)
1184 struct lge_softc *sc;
1185 struct mbuf *m_head;
1186 u_int32_t *txidx;
1187{
1188 struct lge_frag *f = NULL;
1189 struct lge_tx_desc *cur_tx;
1190 struct mbuf *m;
1191 int frag = 0, tot_len = 0;
1192
1193 /*
1194 * Start packing the mbufs in this chain into
1195 * the fragment pointers. Stop when we run out
1196 * of fragments or hit the end of the mbuf chain.
1197 */
1198 m = m_head;
1199 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1200 frag = 0;
1201
1202 for (m = m_head; m != NULL; m = m->m_next) {
1203 if (m->m_len != 0) {
1204 tot_len += m->m_len;
1205 f = &cur_tx->lge_frags[frag];
1206 f->lge_fraglen = m->m_len;
1207 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1208 f->lge_fragptr_hi = 0;
1209 frag++;
1210 }
1211 }
1212
1213 if (m != NULL)
1214 return(ENOBUFS);
1215
1216 cur_tx->lge_mbuf = m_head;
1217 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1218 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1219
1220 /* Queue for transmit */
1221 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1222
1223 return(0);
1224}
1225
1226/*
1227 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1228 * to the mbuf data regions directly in the transmit lists. We also save a
1229 * copy of the pointers since the transmit list fragment pointers are
1230 * physical addresses.
1231 */
1232
1233static void
1234lge_start(ifp)
1235 struct ifnet *ifp;
1236{
1237 struct lge_softc *sc;
1238 struct mbuf *m_head = NULL;
1239 u_int32_t idx;
1240
1241 sc = ifp->if_softc;
1242
1243 if (!sc->lge_link)
1244 return;
1245
1246 idx = sc->lge_cdata.lge_tx_prod;
1247
1248 if (ifp->if_flags & IFF_OACTIVE)
1249 return;
1250
1251 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1252 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1253 break;
1254
1255 IF_DEQUEUE(&ifp->if_snd, m_head);
1256 if (m_head == NULL)
1257 break;
1258
1259 if (lge_encap(sc, m_head, &idx)) {
1260 IF_PREPEND(&ifp->if_snd, m_head);
1261 ifp->if_flags |= IFF_OACTIVE;
1262 break;
1263 }
1264
1265 /*
1266 * If there's a BPF listener, bounce a copy of this frame
1267 * to him.
1268 */
1269 BPF_MTAP(ifp, m_head);
1270 }
1271
1272 sc->lge_cdata.lge_tx_prod = idx;
1273
1274 /*
1275 * Set a timeout in case the chip goes out to lunch.
1276 */
1277 ifp->if_timer = 5;
1278
1279 return;
1280}
1281
1282static void
1283lge_init(xsc)
1284 void *xsc;
1285{
1286 struct lge_softc *sc = xsc;
1287 struct ifnet *ifp = &sc->arpcom.ac_if;
1288 struct mii_data *mii;
1289 int s;
1290
1291 if (ifp->if_flags & IFF_RUNNING)
1292 return;
1293
1294 s = splimp();
1295
1296 /*
1297 * Cancel pending I/O and free all RX/TX buffers.
1298 */
1299 lge_stop(sc);
1300 lge_reset(sc);
1301
1302 mii = device_get_softc(sc->lge_miibus);
1303
1304 /* Set MAC address */
1305 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1306 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1307
1308 /* Init circular RX list. */
1309 if (lge_list_rx_init(sc) == ENOBUFS) {
1310 printf("lge%d: initialization failed: no "
1311 "memory for rx buffers\n", sc->lge_unit);
1312 lge_stop(sc);
1313 (void)splx(s);
1314 return;
1315 }
1316
1317 /*
1318 * Init tx descriptors.
1319 */
1320 lge_list_tx_init(sc);
1321
1322 /* Set initial value for MODE1 register. */
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1324 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1325 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1326 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1327
1328 /* If we want promiscuous mode, set the allframes bit. */
1329 if (ifp->if_flags & IFF_PROMISC) {
1330 CSR_WRITE_4(sc, LGE_MODE1,
1331 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1332 } else {
1333 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1334 }
1335
1336 /*
1337 * Set the capture broadcast bit to capture broadcast frames.
1338 */
1339 if (ifp->if_flags & IFF_BROADCAST) {
1340 CSR_WRITE_4(sc, LGE_MODE1,
1341 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1342 } else {
1343 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1344 }
1345
1346 /* Packet padding workaround? */
1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1348
1349 /* No error frames */
1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1351
1352 /* Receive large frames */
1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1354
1355 /* Workaround: disable RX/TX flow control */
1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1358
1359 /* Make sure to strip CRC from received frames */
1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1361
1362 /* Turn off magic packet mode */
1363 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1364
1365 /* Turn off all VLAN stuff */
1366 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1367 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1368
1369 /* Workarond: FIFO overflow */
1370 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1371 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1372
1373 /*
1374 * Load the multicast filter.
1375 */
1376 lge_setmulti(sc);
1377
1378 /*
1379 * Enable hardware checksum validation for all received IPv4
1380 * packets, do not reject packets with bad checksums.
1381 */
1382 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1383 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1384 LGE_MODE2_RX_ERRCSUM);
1385
1386 /*
1387 * Enable the delivery of PHY interrupts based on
1388 * link/speed/duplex status chalges.
1389 */
1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1391
1392 /* Enable receiver and transmitter. */
1393 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1395
1396 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1397 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1398
1399 /*
1400 * Enable interrupts.
1401 */
1402 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1403 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1404
1405 lge_ifmedia_upd(ifp);
1406
1407 ifp->if_flags |= IFF_RUNNING;
1408 ifp->if_flags &= ~IFF_OACTIVE;
1409
1410 (void)splx(s);
1411
1412 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1413
1414 return;
1415}
1416
1417/*
1418 * Set media options.
1419 */
1420static int
1421lge_ifmedia_upd(ifp)
1422 struct ifnet *ifp;
1423{
1424 struct lge_softc *sc;
1425 struct mii_data *mii;
1426
1427 sc = ifp->if_softc;
1428
1429 mii = device_get_softc(sc->lge_miibus);
1430 sc->lge_link = 0;
1431 if (mii->mii_instance) {
1432 struct mii_softc *miisc;
1433 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1434 miisc = LIST_NEXT(miisc, mii_list))
1435 mii_phy_reset(miisc);
1436 }
1437 mii_mediachg(mii);
1438
1439 return(0);
1440}
1441
1442/*
1443 * Report current media status.
1444 */
1445static void
1446lge_ifmedia_sts(ifp, ifmr)
1447 struct ifnet *ifp;
1448 struct ifmediareq *ifmr;
1449{
1450 struct lge_softc *sc;
1451 struct mii_data *mii;
1452
1453 sc = ifp->if_softc;
1454
1455 mii = device_get_softc(sc->lge_miibus);
1456 mii_pollstat(mii);
1457 ifmr->ifm_active = mii->mii_media_active;
1458 ifmr->ifm_status = mii->mii_media_status;
1459
1460 return;
1461}
1462
1463static int
1464lge_ioctl(ifp, command, data)
1465 struct ifnet *ifp;
1466 u_long command;
1467 caddr_t data;
1468{
1469 struct lge_softc *sc = ifp->if_softc;
1470 struct ifreq *ifr = (struct ifreq *) data;
1471 struct mii_data *mii;
1472 int s, error = 0;
1473
1474 s = splimp();
1475
1476 switch(command) {
1477 case SIOCSIFMTU:
1478 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1479 error = EINVAL;
1480 else
1481 ifp->if_mtu = ifr->ifr_mtu;
1482 break;
1483 case SIOCSIFFLAGS:
1484 if (ifp->if_flags & IFF_UP) {
1485 if (ifp->if_flags & IFF_RUNNING &&
1486 ifp->if_flags & IFF_PROMISC &&
1487 !(sc->lge_if_flags & IFF_PROMISC)) {
1488 CSR_WRITE_4(sc, LGE_MODE1,
1489 LGE_MODE1_SETRST_CTL1|
1490 LGE_MODE1_RX_PROMISC);
1491 } else if (ifp->if_flags & IFF_RUNNING &&
1492 !(ifp->if_flags & IFF_PROMISC) &&
1493 sc->lge_if_flags & IFF_PROMISC) {
1494 CSR_WRITE_4(sc, LGE_MODE1,
1495 LGE_MODE1_RX_PROMISC);
1496 } else {
1497 ifp->if_flags &= ~IFF_RUNNING;
1498 lge_init(sc);
1499 }
1500 } else {
1501 if (ifp->if_flags & IFF_RUNNING)
1502 lge_stop(sc);
1503 }
1504 sc->lge_if_flags = ifp->if_flags;
1505 error = 0;
1506 break;
1507 case SIOCADDMULTI:
1508 case SIOCDELMULTI:
1509 lge_setmulti(sc);
1510 error = 0;
1511 break;
1512 case SIOCGIFMEDIA:
1513 case SIOCSIFMEDIA:
1514 mii = device_get_softc(sc->lge_miibus);
1515 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1516 break;
1517 default:
1518 error = ether_ioctl(ifp, command, data);
1519 break;
1520 }
1521
1522 (void)splx(s);
1523
1524 return(error);
1525}
1526
1527static void
1528lge_watchdog(ifp)
1529 struct ifnet *ifp;
1530{
1531 struct lge_softc *sc;
1532
1533 sc = ifp->if_softc;
1534
1535 ifp->if_oerrors++;
1536 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1537
1538 lge_stop(sc);
1539 lge_reset(sc);
1540 ifp->if_flags &= ~IFF_RUNNING;
1541 lge_init(sc);
1542
1543 if (ifp->if_snd.ifq_head != NULL)
1544 lge_start(ifp);
1545
1546 return;
1547}
1548
1549/*
1550 * Stop the adapter and free any mbufs allocated to the
1551 * RX and TX lists.
1552 */
1553static void
1554lge_stop(sc)
1555 struct lge_softc *sc;
1556{
1557 register int i;
1558 struct ifnet *ifp;
1559
1560 ifp = &sc->arpcom.ac_if;
1561 ifp->if_timer = 0;
1562 untimeout(lge_tick, sc, sc->lge_stat_ch);
1563 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1564
1565 /* Disable receiver and transmitter. */
1566 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1567 sc->lge_link = 0;
1568
1569 /*
1570 * Free data in the RX lists.
1571 */
1572 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1573 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1574 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1575 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1576 }
1577 }
1578 bzero((char *)&sc->lge_ldata->lge_rx_list,
1579 sizeof(sc->lge_ldata->lge_rx_list));
1580
1581 /*
1582 * Free the TX list buffers.
1583 */
1584 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1585 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1586 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1587 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1588 }
1589 }
1590
1591 bzero((char *)&sc->lge_ldata->lge_tx_list,
1592 sizeof(sc->lge_ldata->lge_tx_list));
1593
1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1595
1596 return;
1597}
1598
1599/*
1600 * Stop all chip I/O so that the kernel's probe routines don't
1601 * get confused by errant DMAs when rebooting.
1602 */
1603static void
1604lge_shutdown(dev)
1605 device_t dev;
1606{
1607 struct lge_softc *sc;
1608
1609 sc = device_get_softc(dev);
1610
1611 lge_reset(sc);
1612 lge_stop(sc);
1613
1614 return;
1615}
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 122678 2003-11-14 17:16:58Z obrien $");
36
37/*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
55 *
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
60 * hardware support.
61 *
62 * Special thanks to:
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
70 */
71
72#include <sys/param.h>
73#include <sys/systm.h>
74#include <sys/sockio.h>
75#include <sys/mbuf.h>
76#include <sys/malloc.h>
77#include <sys/kernel.h>
78#include <sys/socket.h>
79
80#include <net/if.h>
81#include <net/if_arp.h>
82#include <net/ethernet.h>
83#include <net/if_dl.h>
84#include <net/if_media.h>
85
86#include <net/bpf.h>
87
88#include <vm/vm.h> /* for vtophys */
89#include <vm/pmap.h> /* for vtophys */
90#include <machine/clock.h> /* for DELAY */
91#include <machine/bus_pio.h>
92#include <machine/bus_memio.h>
93#include <machine/bus.h>
94#include <machine/resource.h>
95#include <sys/bus.h>
96#include <sys/rman.h>
97
98#include <dev/mii/mii.h>
99#include <dev/mii/miivar.h>
100
101#include <dev/pci/pcireg.h>
102#include <dev/pci/pcivar.h>
103
104#define LGE_USEIOSPACE
105
106#include <dev/lge/if_lgereg.h>
107
108/* "controller miibus0" required. See GENERIC if you get errors here. */
109#include "miibus_if.h"
110
111/*
112 * Various supported device vendors/types and their names.
113 */
114static struct lge_type lge_devs[] = {
115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
116 { 0, 0, NULL }
117};
118
119static int lge_probe(device_t);
120static int lge_attach(device_t);
121static int lge_detach(device_t);
122
123static int lge_alloc_jumbo_mem(struct lge_softc *);
124static void lge_free_jumbo_mem(struct lge_softc *);
125static void *lge_jalloc(struct lge_softc *);
126static void lge_jfree(void *, void *);
127
128static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130static void lge_rxeof(struct lge_softc *, int);
131static void lge_rxeoc(struct lge_softc *);
132static void lge_txeof(struct lge_softc *);
133static void lge_intr(void *);
134static void lge_tick(void *);
135static void lge_start(struct ifnet *);
136static int lge_ioctl(struct ifnet *, u_long, caddr_t);
137static void lge_init(void *);
138static void lge_stop(struct lge_softc *);
139static void lge_watchdog(struct ifnet *);
140static void lge_shutdown(device_t);
141static int lge_ifmedia_upd(struct ifnet *);
142static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
143
144static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
145static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
146
147static int lge_miibus_readreg(device_t, int, int);
148static int lge_miibus_writereg(device_t, int, int, int);
149static void lge_miibus_statchg(device_t);
150
151static void lge_setmulti(struct lge_softc *);
152static u_int32_t lge_mchash(caddr_t);
153static void lge_reset(struct lge_softc *);
154static int lge_list_rx_init(struct lge_softc *);
155static int lge_list_tx_init(struct lge_softc *);
156
157#ifdef LGE_USEIOSPACE
158#define LGE_RES SYS_RES_IOPORT
159#define LGE_RID LGE_PCI_LOIO
160#else
161#define LGE_RES SYS_RES_MEMORY
162#define LGE_RID LGE_PCI_LOMEM
163#endif
164
165static device_method_t lge_methods[] = {
166 /* Device interface */
167 DEVMETHOD(device_probe, lge_probe),
168 DEVMETHOD(device_attach, lge_attach),
169 DEVMETHOD(device_detach, lge_detach),
170 DEVMETHOD(device_shutdown, lge_shutdown),
171
172 /* bus interface */
173 DEVMETHOD(bus_print_child, bus_generic_print_child),
174 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
175
176 /* MII interface */
177 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
178 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
179 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
180
181 { 0, 0 }
182};
183
184static driver_t lge_driver = {
185 "lge",
186 lge_methods,
187 sizeof(struct lge_softc)
188};
189
190static devclass_t lge_devclass;
191
192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0);
193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
194MODULE_DEPEND(lge, pci, 1, 1, 1);
195MODULE_DEPEND(lge, ether, 1, 1, 1);
196MODULE_DEPEND(lge, miibus, 1, 1, 1);
197
198#define LGE_SETBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) | (x))
201
202#define LGE_CLRBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, \
204 CSR_READ_4(sc, reg) & ~(x))
205
206#define SIO_SET(x) \
207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208
209#define SIO_CLR(x) \
210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
211
212/*
213 * Read a word of data stored in the EEPROM at address 'addr.'
214 */
215static void
216lge_eeprom_getword(sc, addr, dest)
217 struct lge_softc *sc;
218 int addr;
219 u_int16_t *dest;
220{
221 register int i;
222 u_int32_t val;
223
224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
226
227 for (i = 0; i < LGE_TIMEOUT; i++)
228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
229 break;
230
231 if (i == LGE_TIMEOUT) {
232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
233 return;
234 }
235
236 val = CSR_READ_4(sc, LGE_EEDATA);
237
238 if (addr & 1)
239 *dest = (val >> 16) & 0xFFFF;
240 else
241 *dest = val & 0xFFFF;
242
243 return;
244}
245
246/*
247 * Read a sequence of words from the EEPROM.
248 */
249static void
250lge_read_eeprom(sc, dest, off, cnt, swap)
251 struct lge_softc *sc;
252 caddr_t dest;
253 int off;
254 int cnt;
255 int swap;
256{
257 int i;
258 u_int16_t word = 0, *ptr;
259
260 for (i = 0; i < cnt; i++) {
261 lge_eeprom_getword(sc, off + i, &word);
262 ptr = (u_int16_t *)(dest + (i * 2));
263 if (swap)
264 *ptr = ntohs(word);
265 else
266 *ptr = word;
267 }
268
269 return;
270}
271
272static int
273lge_miibus_readreg(dev, phy, reg)
274 device_t dev;
275 int phy, reg;
276{
277 struct lge_softc *sc;
278 int i;
279
280 sc = device_get_softc(dev);
281
282 /*
283 * If we have a non-PCS PHY, pretend that the internal
284 * autoneg stuff at PHY address 0 isn't there so that
285 * the miibus code will find only the GMII PHY.
286 */
287 if (sc->lge_pcs == 0 && phy == 0)
288 return(0);
289
290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
291
292 for (i = 0; i < LGE_TIMEOUT; i++)
293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
294 break;
295
296 if (i == LGE_TIMEOUT) {
297 printf("lge%d: PHY read timed out\n", sc->lge_unit);
298 return(0);
299 }
300
301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
302}
303
304static int
305lge_miibus_writereg(dev, phy, reg, data)
306 device_t dev;
307 int phy, reg, data;
308{
309 struct lge_softc *sc;
310 int i;
311
312 sc = device_get_softc(dev);
313
314 CSR_WRITE_4(sc, LGE_GMIICTL,
315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
316
317 for (i = 0; i < LGE_TIMEOUT; i++)
318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
319 break;
320
321 if (i == LGE_TIMEOUT) {
322 printf("lge%d: PHY write timed out\n", sc->lge_unit);
323 return(0);
324 }
325
326 return(0);
327}
328
329static void
330lge_miibus_statchg(dev)
331 device_t dev;
332{
333 struct lge_softc *sc;
334 struct mii_data *mii;
335
336 sc = device_get_softc(dev);
337 mii = device_get_softc(sc->lge_miibus);
338
339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
340 switch (IFM_SUBTYPE(mii->mii_media_active)) {
341 case IFM_1000_T:
342 case IFM_1000_SX:
343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
344 break;
345 case IFM_100_TX:
346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
347 break;
348 case IFM_10_T:
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
350 break;
351 default:
352 /*
353 * Choose something, even if it's wrong. Clearing
354 * all the bits will hose autoneg on the internal
355 * PHY.
356 */
357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
358 break;
359 }
360
361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
363 } else {
364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
365 }
366
367 return;
368}
369
370static u_int32_t
371lge_mchash(addr)
372 caddr_t addr;
373{
374 u_int32_t crc, carry;
375 int idx, bit;
376 u_int8_t data;
377
378 /* Compute CRC for the address value. */
379 crc = 0xFFFFFFFF; /* initial value */
380
381 for (idx = 0; idx < 6; idx++) {
382 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
383 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
384 crc <<= 1;
385 if (carry)
386 crc = (crc ^ 0x04c11db6) | carry;
387 }
388 }
389
390 /*
391 * return the filter bit position
392 */
393 return((crc >> 26) & 0x0000003F);
394}
395
396static void
397lge_setmulti(sc)
398 struct lge_softc *sc;
399{
400 struct ifnet *ifp;
401 struct ifmultiaddr *ifma;
402 u_int32_t h = 0, hashes[2] = { 0, 0 };
403
404 ifp = &sc->arpcom.ac_if;
405
406 /* Make sure multicast hash table is enabled. */
407 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
408
409 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
410 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
411 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
412 return;
413 }
414
415 /* first, zot all the existing hash bits */
416 CSR_WRITE_4(sc, LGE_MAR0, 0);
417 CSR_WRITE_4(sc, LGE_MAR1, 0);
418
419 /* now program new ones */
420 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
421 if (ifma->ifma_addr->sa_family != AF_LINK)
422 continue;
423 h = lge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
424 if (h < 32)
425 hashes[0] |= (1 << h);
426 else
427 hashes[1] |= (1 << (h - 32));
428 }
429
430 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
431 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
432
433 return;
434}
435
436static void
437lge_reset(sc)
438 struct lge_softc *sc;
439{
440 register int i;
441
442 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
443
444 for (i = 0; i < LGE_TIMEOUT; i++) {
445 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
446 break;
447 }
448
449 if (i == LGE_TIMEOUT)
450 printf("lge%d: reset never completed\n", sc->lge_unit);
451
452 /* Wait a little while for the chip to get its brains in order. */
453 DELAY(1000);
454
455 return;
456}
457
458/*
459 * Probe for a Level 1 chip. Check the PCI vendor and device
460 * IDs against our list and return a device name if we find a match.
461 */
462static int
463lge_probe(dev)
464 device_t dev;
465{
466 struct lge_type *t;
467
468 t = lge_devs;
469
470 while(t->lge_name != NULL) {
471 if ((pci_get_vendor(dev) == t->lge_vid) &&
472 (pci_get_device(dev) == t->lge_did)) {
473 device_set_desc(dev, t->lge_name);
474 return(0);
475 }
476 t++;
477 }
478
479 return(ENXIO);
480}
481
482/*
483 * Attach the interface. Allocate softc structures, do ifmedia
484 * setup and ethernet/BPF attach.
485 */
486static int
487lge_attach(dev)
488 device_t dev;
489{
490 int s;
491 u_char eaddr[ETHER_ADDR_LEN];
492 struct lge_softc *sc;
493 struct ifnet *ifp;
494 int unit, error = 0, rid;
495
496 s = splimp();
497
498 sc = device_get_softc(dev);
499 unit = device_get_unit(dev);
500 bzero(sc, sizeof(struct lge_softc));
501#ifndef BURN_BRIDGES
502 /*
503 * Handle power management nonsense.
504 */
505 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
506 u_int32_t iobase, membase, irq;
507
508 /* Save important PCI config data. */
509 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
510 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
511 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
512
513 /* Reset the power state. */
514 printf("lge%d: chip is in D%d power mode "
515 "-- setting to D0\n", unit,
516 pci_get_powerstate(dev));
517 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
518
519 /* Restore PCI config data. */
520 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
521 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
522 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
523 }
524#endif
525 /*
526 * Map control/status registers.
527 */
528 pci_enable_busmaster(dev);
529
530 rid = LGE_RID;
531 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
532 0, ~0, 1, RF_ACTIVE);
533
534 if (sc->lge_res == NULL) {
535 printf("lge%d: couldn't map ports/memory\n", unit);
536 error = ENXIO;
537 goto fail;
538 }
539
540 sc->lge_btag = rman_get_bustag(sc->lge_res);
541 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
542
543 /* Allocate interrupt */
544 rid = 0;
545 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
546 RF_SHAREABLE | RF_ACTIVE);
547
548 if (sc->lge_irq == NULL) {
549 printf("lge%d: couldn't map interrupt\n", unit);
550 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
551 error = ENXIO;
552 goto fail;
553 }
554
555 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
556 lge_intr, sc, &sc->lge_intrhand);
557
558 if (error) {
559 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
560 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
561 printf("lge%d: couldn't set up irq\n", unit);
562 goto fail;
563 }
564
565 /* Reset the adapter. */
566 lge_reset(sc);
567
568 /*
569 * Get station address from the EEPROM.
570 */
571 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
572 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
573 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
574
575 /*
576 * A Level 1 chip was detected. Inform the world.
577 */
578 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
579
580 sc->lge_unit = unit;
581 callout_handle_init(&sc->lge_stat_ch);
582 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
583
584 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
585 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
586
587 if (sc->lge_ldata == NULL) {
588 printf("lge%d: no memory for list buffers!\n", unit);
589 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
592 error = ENXIO;
593 goto fail;
594 }
595 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
596
597 /* Try to allocate memory for jumbo buffers. */
598 if (lge_alloc_jumbo_mem(sc)) {
599 printf("lge%d: jumbo buffer allocation failed\n",
600 sc->lge_unit);
601 contigfree(sc->lge_ldata,
602 sizeof(struct lge_list_data), M_DEVBUF);
603 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
605 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
606 error = ENXIO;
607 goto fail;
608 }
609
610 ifp = &sc->arpcom.ac_if;
611 ifp->if_softc = sc;
612 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
613 ifp->if_mtu = ETHERMTU;
614 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
615 ifp->if_ioctl = lge_ioctl;
616 ifp->if_output = ether_output;
617 ifp->if_start = lge_start;
618 ifp->if_watchdog = lge_watchdog;
619 ifp->if_init = lge_init;
620 ifp->if_baudrate = 1000000000;
621 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
622 ifp->if_capabilities = IFCAP_RXCSUM;
623 ifp->if_capenable = ifp->if_capabilities;
624
625 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
626 sc->lge_pcs = 1;
627 else
628 sc->lge_pcs = 0;
629
630 /*
631 * Do MII setup.
632 */
633 if (mii_phy_probe(dev, &sc->lge_miibus,
634 lge_ifmedia_upd, lge_ifmedia_sts)) {
635 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
636 contigfree(sc->lge_ldata,
637 sizeof(struct lge_list_data), M_DEVBUF);
638 lge_free_jumbo_mem(sc);
639 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
640 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
641 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
642 error = ENXIO;
643 goto fail;
644 }
645
646 /*
647 * Call MI attach routine.
648 */
649 ether_ifattach(ifp, eaddr);
650 callout_handle_init(&sc->lge_stat_ch);
651
652fail:
653 splx(s);
654 return(error);
655}
656
657static int
658lge_detach(dev)
659 device_t dev;
660{
661 struct lge_softc *sc;
662 struct ifnet *ifp;
663 int s;
664
665 s = splimp();
666
667 sc = device_get_softc(dev);
668 ifp = &sc->arpcom.ac_if;
669
670 lge_reset(sc);
671 lge_stop(sc);
672 ether_ifdetach(ifp);
673
674 bus_generic_detach(dev);
675 device_delete_child(dev, sc->lge_miibus);
676
677 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
679 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
680
681 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
682 lge_free_jumbo_mem(sc);
683
684 splx(s);
685
686 return(0);
687}
688
689/*
690 * Initialize the transmit descriptors.
691 */
692static int
693lge_list_tx_init(sc)
694 struct lge_softc *sc;
695{
696 struct lge_list_data *ld;
697 struct lge_ring_data *cd;
698 int i;
699
700 cd = &sc->lge_cdata;
701 ld = sc->lge_ldata;
702 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
703 ld->lge_tx_list[i].lge_mbuf = NULL;
704 ld->lge_tx_list[i].lge_ctl = 0;
705 }
706
707 cd->lge_tx_prod = cd->lge_tx_cons = 0;
708
709 return(0);
710}
711
712
713/*
714 * Initialize the RX descriptors and allocate mbufs for them. Note that
715 * we arralge the descriptors in a closed ring, so that the last descriptor
716 * points back to the first.
717 */
718static int
719lge_list_rx_init(sc)
720 struct lge_softc *sc;
721{
722 struct lge_list_data *ld;
723 struct lge_ring_data *cd;
724 int i;
725
726 ld = sc->lge_ldata;
727 cd = &sc->lge_cdata;
728
729 cd->lge_rx_prod = cd->lge_rx_cons = 0;
730
731 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
732
733 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
734 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
735 break;
736 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
737 return(ENOBUFS);
738 }
739
740 /* Clear possible 'rx command queue empty' interrupt. */
741 CSR_READ_4(sc, LGE_ISR);
742
743 return(0);
744}
745
746/*
747 * Initialize an RX descriptor and attach an MBUF cluster.
748 */
749static int
750lge_newbuf(sc, c, m)
751 struct lge_softc *sc;
752 struct lge_rx_desc *c;
753 struct mbuf *m;
754{
755 struct mbuf *m_new = NULL;
756 caddr_t *buf = NULL;
757
758 if (m == NULL) {
759 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
760 if (m_new == NULL) {
761 printf("lge%d: no memory for rx list "
762 "-- packet dropped!\n", sc->lge_unit);
763 return(ENOBUFS);
764 }
765
766 /* Allocate the jumbo buffer */
767 buf = lge_jalloc(sc);
768 if (buf == NULL) {
769#ifdef LGE_VERBOSE
770 printf("lge%d: jumbo allocation failed "
771 "-- packet dropped!\n", sc->lge_unit);
772#endif
773 m_freem(m_new);
774 return(ENOBUFS);
775 }
776 /* Attach the buffer to the mbuf */
777 m_new->m_data = (void *)buf;
778 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
779 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree,
780 (struct lge_softc *)sc, 0, EXT_NET_DRV);
781 } else {
782 m_new = m;
783 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
784 m_new->m_data = m_new->m_ext.ext_buf;
785 }
786
787 /*
788 * Adjust alignment so packet payload begins on a
789 * longword boundary. Mandatory for Alpha, useful on
790 * x86 too.
791 */
792 m_adj(m_new, ETHER_ALIGN);
793
794 c->lge_mbuf = m_new;
795 c->lge_fragptr_hi = 0;
796 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
797 c->lge_fraglen = m_new->m_len;
798 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
799 c->lge_sts = 0;
800
801 /*
802 * Put this buffer in the RX command FIFO. To do this,
803 * we just write the physical address of the descriptor
804 * into the RX descriptor address registers. Note that
805 * there are two registers, one high DWORD and one low
806 * DWORD, which lets us specify a 64-bit address if
807 * desired. We only use a 32-bit address for now.
808 * Writing to the low DWORD register is what actually
809 * causes the command to be issued, so we do that
810 * last.
811 */
812 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
813 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
814
815 return(0);
816}
817
818static int
819lge_alloc_jumbo_mem(sc)
820 struct lge_softc *sc;
821{
822 caddr_t ptr;
823 register int i;
824 struct lge_jpool_entry *entry;
825
826 /* Grab a big chunk o' storage. */
827 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
828 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
829
830 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
831 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
832 return(ENOBUFS);
833 }
834
835 SLIST_INIT(&sc->lge_jfree_listhead);
836 SLIST_INIT(&sc->lge_jinuse_listhead);
837
838 /*
839 * Now divide it up into 9K pieces and save the addresses
840 * in an array.
841 */
842 ptr = sc->lge_cdata.lge_jumbo_buf;
843 for (i = 0; i < LGE_JSLOTS; i++) {
844 sc->lge_cdata.lge_jslots[i] = ptr;
845 ptr += LGE_JLEN;
846 entry = malloc(sizeof(struct lge_jpool_entry),
847 M_DEVBUF, M_NOWAIT);
848 if (entry == NULL) {
849 printf("lge%d: no memory for jumbo "
850 "buffer queue!\n", sc->lge_unit);
851 return(ENOBUFS);
852 }
853 entry->slot = i;
854 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
855 entry, jpool_entries);
856 }
857
858 return(0);
859}
860
861static void
862lge_free_jumbo_mem(sc)
863 struct lge_softc *sc;
864{
865 int i;
866 struct lge_jpool_entry *entry;
867
868 for (i = 0; i < LGE_JSLOTS; i++) {
869 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
870 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
871 free(entry, M_DEVBUF);
872 }
873
874 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
875
876 return;
877}
878
879/*
880 * Allocate a jumbo buffer.
881 */
882static void *
883lge_jalloc(sc)
884 struct lge_softc *sc;
885{
886 struct lge_jpool_entry *entry;
887
888 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
889
890 if (entry == NULL) {
891#ifdef LGE_VERBOSE
892 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
893#endif
894 return(NULL);
895 }
896
897 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
898 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
899 return(sc->lge_cdata.lge_jslots[entry->slot]);
900}
901
902/*
903 * Release a jumbo buffer.
904 */
905static void
906lge_jfree(buf, args)
907 void *buf;
908 void *args;
909{
910 struct lge_softc *sc;
911 int i;
912 struct lge_jpool_entry *entry;
913
914 /* Extract the softc struct pointer. */
915 sc = args;
916
917 if (sc == NULL)
918 panic("lge_jfree: can't find softc pointer!");
919
920 /* calculate the slot this buffer belongs to */
921 i = ((vm_offset_t)buf
922 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
923
924 if ((i < 0) || (i >= LGE_JSLOTS))
925 panic("lge_jfree: asked to free buffer that we don't manage!");
926
927 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
928 if (entry == NULL)
929 panic("lge_jfree: buffer not in use!");
930 entry->slot = i;
931 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
932 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
933
934 return;
935}
936
937/*
938 * A frame has been uploaded: pass the resulting mbuf chain up to
939 * the higher level protocols.
940 */
941static void
942lge_rxeof(sc, cnt)
943 struct lge_softc *sc;
944 int cnt;
945{
946 struct mbuf *m;
947 struct ifnet *ifp;
948 struct lge_rx_desc *cur_rx;
949 int c, i, total_len = 0;
950 u_int32_t rxsts, rxctl;
951
952 ifp = &sc->arpcom.ac_if;
953
954 /* Find out how many frames were processed. */
955 c = cnt;
956 i = sc->lge_cdata.lge_rx_cons;
957
958 /* Suck them in. */
959 while(c) {
960 struct mbuf *m0 = NULL;
961
962 cur_rx = &sc->lge_ldata->lge_rx_list[i];
963 rxctl = cur_rx->lge_ctl;
964 rxsts = cur_rx->lge_sts;
965 m = cur_rx->lge_mbuf;
966 cur_rx->lge_mbuf = NULL;
967 total_len = LGE_RXBYTES(cur_rx);
968 LGE_INC(i, LGE_RX_LIST_CNT);
969 c--;
970
971 /*
972 * If an error occurs, update stats, clear the
973 * status word and leave the mbuf cluster in place:
974 * it should simply get re-used next time this descriptor
975 * comes up in the ring.
976 */
977 if (rxctl & LGE_RXCTL_ERRMASK) {
978 ifp->if_ierrors++;
979 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
980 continue;
981 }
982
983 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
984 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
985 ifp, NULL);
986 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
987 if (m0 == NULL) {
988 printf("lge%d: no receive buffers "
989 "available -- packet dropped!\n",
990 sc->lge_unit);
991 ifp->if_ierrors++;
992 continue;
993 }
994 m = m0;
995 } else {
996 m->m_pkthdr.rcvif = ifp;
997 m->m_pkthdr.len = m->m_len = total_len;
998 }
999
1000 ifp->if_ipackets++;
1001
1002 /* Do IP checksum checking. */
1003 if (rxsts & LGE_RXSTS_ISIP)
1004 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1005 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1006 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1007 if ((rxsts & LGE_RXSTS_ISTCP &&
1008 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1009 (rxsts & LGE_RXSTS_ISUDP &&
1010 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1011 m->m_pkthdr.csum_flags |=
1012 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1013 m->m_pkthdr.csum_data = 0xffff;
1014 }
1015
1016 (*ifp->if_input)(ifp, m);
1017 }
1018
1019 sc->lge_cdata.lge_rx_cons = i;
1020
1021 return;
1022}
1023
1024static void
1025lge_rxeoc(sc)
1026 struct lge_softc *sc;
1027{
1028 struct ifnet *ifp;
1029
1030 ifp = &sc->arpcom.ac_if;
1031 ifp->if_flags &= ~IFF_RUNNING;
1032 lge_init(sc);
1033 return;
1034}
1035
1036/*
1037 * A frame was downloaded to the chip. It's safe for us to clean up
1038 * the list buffers.
1039 */
1040
1041static void
1042lge_txeof(sc)
1043 struct lge_softc *sc;
1044{
1045 struct lge_tx_desc *cur_tx = NULL;
1046 struct ifnet *ifp;
1047 u_int32_t idx, txdone;
1048
1049 ifp = &sc->arpcom.ac_if;
1050
1051 /* Clear the timeout timer. */
1052 ifp->if_timer = 0;
1053
1054 /*
1055 * Go through our tx list and free mbufs for those
1056 * frames that have been transmitted.
1057 */
1058 idx = sc->lge_cdata.lge_tx_cons;
1059 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1060
1061 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1062 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1063
1064 ifp->if_opackets++;
1065 if (cur_tx->lge_mbuf != NULL) {
1066 m_freem(cur_tx->lge_mbuf);
1067 cur_tx->lge_mbuf = NULL;
1068 }
1069 cur_tx->lge_ctl = 0;
1070
1071 txdone--;
1072 LGE_INC(idx, LGE_TX_LIST_CNT);
1073 ifp->if_timer = 0;
1074 }
1075
1076 sc->lge_cdata.lge_tx_cons = idx;
1077
1078 if (cur_tx != NULL)
1079 ifp->if_flags &= ~IFF_OACTIVE;
1080
1081 return;
1082}
1083
1084static void
1085lge_tick(xsc)
1086 void *xsc;
1087{
1088 struct lge_softc *sc;
1089 struct mii_data *mii;
1090 struct ifnet *ifp;
1091 int s;
1092
1093 s = splimp();
1094
1095 sc = xsc;
1096 ifp = &sc->arpcom.ac_if;
1097
1098 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1099 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1100 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1101 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1102
1103 if (!sc->lge_link) {
1104 mii = device_get_softc(sc->lge_miibus);
1105 mii_tick(mii);
1106 if (mii->mii_media_status & IFM_ACTIVE &&
1107 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1108 sc->lge_link++;
1109 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1110 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1111 printf("lge%d: gigabit link up\n",
1112 sc->lge_unit);
1113 if (ifp->if_snd.ifq_head != NULL)
1114 lge_start(ifp);
1115 }
1116 }
1117
1118 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1119
1120 splx(s);
1121
1122 return;
1123}
1124
1125static void
1126lge_intr(arg)
1127 void *arg;
1128{
1129 struct lge_softc *sc;
1130 struct ifnet *ifp;
1131 u_int32_t status;
1132
1133 sc = arg;
1134 ifp = &sc->arpcom.ac_if;
1135
1136 /* Supress unwanted interrupts */
1137 if (!(ifp->if_flags & IFF_UP)) {
1138 lge_stop(sc);
1139 return;
1140 }
1141
1142 for (;;) {
1143 /*
1144 * Reading the ISR register clears all interrupts, and
1145 * clears the 'interrupts enabled' bit in the IMR
1146 * register.
1147 */
1148 status = CSR_READ_4(sc, LGE_ISR);
1149
1150 if ((status & LGE_INTRS) == 0)
1151 break;
1152
1153 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1154 lge_txeof(sc);
1155
1156 if (status & LGE_ISR_RXDMA_DONE)
1157 lge_rxeof(sc, LGE_RX_DMACNT(status));
1158
1159 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1160 lge_rxeoc(sc);
1161
1162 if (status & LGE_ISR_PHY_INTR) {
1163 sc->lge_link = 0;
1164 untimeout(lge_tick, sc, sc->lge_stat_ch);
1165 lge_tick(sc);
1166 }
1167 }
1168
1169 /* Re-enable interrupts. */
1170 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1171
1172 if (ifp->if_snd.ifq_head != NULL)
1173 lge_start(ifp);
1174
1175 return;
1176}
1177
1178/*
1179 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1180 * pointers to the fragment pointers.
1181 */
1182static int
1183lge_encap(sc, m_head, txidx)
1184 struct lge_softc *sc;
1185 struct mbuf *m_head;
1186 u_int32_t *txidx;
1187{
1188 struct lge_frag *f = NULL;
1189 struct lge_tx_desc *cur_tx;
1190 struct mbuf *m;
1191 int frag = 0, tot_len = 0;
1192
1193 /*
1194 * Start packing the mbufs in this chain into
1195 * the fragment pointers. Stop when we run out
1196 * of fragments or hit the end of the mbuf chain.
1197 */
1198 m = m_head;
1199 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1200 frag = 0;
1201
1202 for (m = m_head; m != NULL; m = m->m_next) {
1203 if (m->m_len != 0) {
1204 tot_len += m->m_len;
1205 f = &cur_tx->lge_frags[frag];
1206 f->lge_fraglen = m->m_len;
1207 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1208 f->lge_fragptr_hi = 0;
1209 frag++;
1210 }
1211 }
1212
1213 if (m != NULL)
1214 return(ENOBUFS);
1215
1216 cur_tx->lge_mbuf = m_head;
1217 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1218 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1219
1220 /* Queue for transmit */
1221 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1222
1223 return(0);
1224}
1225
1226/*
1227 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1228 * to the mbuf data regions directly in the transmit lists. We also save a
1229 * copy of the pointers since the transmit list fragment pointers are
1230 * physical addresses.
1231 */
1232
1233static void
1234lge_start(ifp)
1235 struct ifnet *ifp;
1236{
1237 struct lge_softc *sc;
1238 struct mbuf *m_head = NULL;
1239 u_int32_t idx;
1240
1241 sc = ifp->if_softc;
1242
1243 if (!sc->lge_link)
1244 return;
1245
1246 idx = sc->lge_cdata.lge_tx_prod;
1247
1248 if (ifp->if_flags & IFF_OACTIVE)
1249 return;
1250
1251 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1252 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1253 break;
1254
1255 IF_DEQUEUE(&ifp->if_snd, m_head);
1256 if (m_head == NULL)
1257 break;
1258
1259 if (lge_encap(sc, m_head, &idx)) {
1260 IF_PREPEND(&ifp->if_snd, m_head);
1261 ifp->if_flags |= IFF_OACTIVE;
1262 break;
1263 }
1264
1265 /*
1266 * If there's a BPF listener, bounce a copy of this frame
1267 * to him.
1268 */
1269 BPF_MTAP(ifp, m_head);
1270 }
1271
1272 sc->lge_cdata.lge_tx_prod = idx;
1273
1274 /*
1275 * Set a timeout in case the chip goes out to lunch.
1276 */
1277 ifp->if_timer = 5;
1278
1279 return;
1280}
1281
1282static void
1283lge_init(xsc)
1284 void *xsc;
1285{
1286 struct lge_softc *sc = xsc;
1287 struct ifnet *ifp = &sc->arpcom.ac_if;
1288 struct mii_data *mii;
1289 int s;
1290
1291 if (ifp->if_flags & IFF_RUNNING)
1292 return;
1293
1294 s = splimp();
1295
1296 /*
1297 * Cancel pending I/O and free all RX/TX buffers.
1298 */
1299 lge_stop(sc);
1300 lge_reset(sc);
1301
1302 mii = device_get_softc(sc->lge_miibus);
1303
1304 /* Set MAC address */
1305 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1306 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1307
1308 /* Init circular RX list. */
1309 if (lge_list_rx_init(sc) == ENOBUFS) {
1310 printf("lge%d: initialization failed: no "
1311 "memory for rx buffers\n", sc->lge_unit);
1312 lge_stop(sc);
1313 (void)splx(s);
1314 return;
1315 }
1316
1317 /*
1318 * Init tx descriptors.
1319 */
1320 lge_list_tx_init(sc);
1321
1322 /* Set initial value for MODE1 register. */
1323 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1324 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1325 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1326 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1327
1328 /* If we want promiscuous mode, set the allframes bit. */
1329 if (ifp->if_flags & IFF_PROMISC) {
1330 CSR_WRITE_4(sc, LGE_MODE1,
1331 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1332 } else {
1333 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1334 }
1335
1336 /*
1337 * Set the capture broadcast bit to capture broadcast frames.
1338 */
1339 if (ifp->if_flags & IFF_BROADCAST) {
1340 CSR_WRITE_4(sc, LGE_MODE1,
1341 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1342 } else {
1343 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1344 }
1345
1346 /* Packet padding workaround? */
1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1348
1349 /* No error frames */
1350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1351
1352 /* Receive large frames */
1353 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1354
1355 /* Workaround: disable RX/TX flow control */
1356 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1358
1359 /* Make sure to strip CRC from received frames */
1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1361
1362 /* Turn off magic packet mode */
1363 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1364
1365 /* Turn off all VLAN stuff */
1366 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1367 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1368
1369 /* Workarond: FIFO overflow */
1370 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1371 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1372
1373 /*
1374 * Load the multicast filter.
1375 */
1376 lge_setmulti(sc);
1377
1378 /*
1379 * Enable hardware checksum validation for all received IPv4
1380 * packets, do not reject packets with bad checksums.
1381 */
1382 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1383 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1384 LGE_MODE2_RX_ERRCSUM);
1385
1386 /*
1387 * Enable the delivery of PHY interrupts based on
1388 * link/speed/duplex status chalges.
1389 */
1390 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1391
1392 /* Enable receiver and transmitter. */
1393 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1395
1396 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1397 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1398
1399 /*
1400 * Enable interrupts.
1401 */
1402 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1403 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1404
1405 lge_ifmedia_upd(ifp);
1406
1407 ifp->if_flags |= IFF_RUNNING;
1408 ifp->if_flags &= ~IFF_OACTIVE;
1409
1410 (void)splx(s);
1411
1412 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1413
1414 return;
1415}
1416
1417/*
1418 * Set media options.
1419 */
1420static int
1421lge_ifmedia_upd(ifp)
1422 struct ifnet *ifp;
1423{
1424 struct lge_softc *sc;
1425 struct mii_data *mii;
1426
1427 sc = ifp->if_softc;
1428
1429 mii = device_get_softc(sc->lge_miibus);
1430 sc->lge_link = 0;
1431 if (mii->mii_instance) {
1432 struct mii_softc *miisc;
1433 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1434 miisc = LIST_NEXT(miisc, mii_list))
1435 mii_phy_reset(miisc);
1436 }
1437 mii_mediachg(mii);
1438
1439 return(0);
1440}
1441
1442/*
1443 * Report current media status.
1444 */
1445static void
1446lge_ifmedia_sts(ifp, ifmr)
1447 struct ifnet *ifp;
1448 struct ifmediareq *ifmr;
1449{
1450 struct lge_softc *sc;
1451 struct mii_data *mii;
1452
1453 sc = ifp->if_softc;
1454
1455 mii = device_get_softc(sc->lge_miibus);
1456 mii_pollstat(mii);
1457 ifmr->ifm_active = mii->mii_media_active;
1458 ifmr->ifm_status = mii->mii_media_status;
1459
1460 return;
1461}
1462
1463static int
1464lge_ioctl(ifp, command, data)
1465 struct ifnet *ifp;
1466 u_long command;
1467 caddr_t data;
1468{
1469 struct lge_softc *sc = ifp->if_softc;
1470 struct ifreq *ifr = (struct ifreq *) data;
1471 struct mii_data *mii;
1472 int s, error = 0;
1473
1474 s = splimp();
1475
1476 switch(command) {
1477 case SIOCSIFMTU:
1478 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1479 error = EINVAL;
1480 else
1481 ifp->if_mtu = ifr->ifr_mtu;
1482 break;
1483 case SIOCSIFFLAGS:
1484 if (ifp->if_flags & IFF_UP) {
1485 if (ifp->if_flags & IFF_RUNNING &&
1486 ifp->if_flags & IFF_PROMISC &&
1487 !(sc->lge_if_flags & IFF_PROMISC)) {
1488 CSR_WRITE_4(sc, LGE_MODE1,
1489 LGE_MODE1_SETRST_CTL1|
1490 LGE_MODE1_RX_PROMISC);
1491 } else if (ifp->if_flags & IFF_RUNNING &&
1492 !(ifp->if_flags & IFF_PROMISC) &&
1493 sc->lge_if_flags & IFF_PROMISC) {
1494 CSR_WRITE_4(sc, LGE_MODE1,
1495 LGE_MODE1_RX_PROMISC);
1496 } else {
1497 ifp->if_flags &= ~IFF_RUNNING;
1498 lge_init(sc);
1499 }
1500 } else {
1501 if (ifp->if_flags & IFF_RUNNING)
1502 lge_stop(sc);
1503 }
1504 sc->lge_if_flags = ifp->if_flags;
1505 error = 0;
1506 break;
1507 case SIOCADDMULTI:
1508 case SIOCDELMULTI:
1509 lge_setmulti(sc);
1510 error = 0;
1511 break;
1512 case SIOCGIFMEDIA:
1513 case SIOCSIFMEDIA:
1514 mii = device_get_softc(sc->lge_miibus);
1515 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1516 break;
1517 default:
1518 error = ether_ioctl(ifp, command, data);
1519 break;
1520 }
1521
1522 (void)splx(s);
1523
1524 return(error);
1525}
1526
1527static void
1528lge_watchdog(ifp)
1529 struct ifnet *ifp;
1530{
1531 struct lge_softc *sc;
1532
1533 sc = ifp->if_softc;
1534
1535 ifp->if_oerrors++;
1536 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1537
1538 lge_stop(sc);
1539 lge_reset(sc);
1540 ifp->if_flags &= ~IFF_RUNNING;
1541 lge_init(sc);
1542
1543 if (ifp->if_snd.ifq_head != NULL)
1544 lge_start(ifp);
1545
1546 return;
1547}
1548
1549/*
1550 * Stop the adapter and free any mbufs allocated to the
1551 * RX and TX lists.
1552 */
1553static void
1554lge_stop(sc)
1555 struct lge_softc *sc;
1556{
1557 register int i;
1558 struct ifnet *ifp;
1559
1560 ifp = &sc->arpcom.ac_if;
1561 ifp->if_timer = 0;
1562 untimeout(lge_tick, sc, sc->lge_stat_ch);
1563 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1564
1565 /* Disable receiver and transmitter. */
1566 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1567 sc->lge_link = 0;
1568
1569 /*
1570 * Free data in the RX lists.
1571 */
1572 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1573 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1574 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1575 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1576 }
1577 }
1578 bzero((char *)&sc->lge_ldata->lge_rx_list,
1579 sizeof(sc->lge_ldata->lge_rx_list));
1580
1581 /*
1582 * Free the TX list buffers.
1583 */
1584 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1585 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1586 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1587 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1588 }
1589 }
1590
1591 bzero((char *)&sc->lge_ldata->lge_tx_list,
1592 sizeof(sc->lge_ldata->lge_tx_list));
1593
1594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1595
1596 return;
1597}
1598
1599/*
1600 * Stop all chip I/O so that the kernel's probe routines don't
1601 * get confused by errant DMAs when rebooting.
1602 */
1603static void
1604lge_shutdown(dev)
1605 device_t dev;
1606{
1607 struct lge_softc *sc;
1608
1609 sc = device_get_softc(dev);
1610
1611 lge_reset(sc);
1612 lge_stop(sc);
1613
1614 return;
1615}