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e1000_80003es2lan.c (205869) e1000_80003es2lan.c (218588)
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 205869 2010-03-29 23:36:34Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 218588 2011-02-12 00:07:40Z jfv $*/
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41

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77static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80/*
81 * A table for the GG82563 cable length where the range is defined
82 * with a lower bound at "index" and the upper bound at
83 * "index + 5".
84 */
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41

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77static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80/*
81 * A table for the GG82563 cable length where the range is defined
82 * with a lower bound at "index" and the upper bound at
83 * "index + 5".
84 */
85static const u16 e1000_gg82563_cable_length_table[] =
86 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
85static const u16 e1000_gg82563_cable_length_table[] = {
86 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
87#define GG82563_CABLE_LENGTH_TABLE_SIZE \
88 (sizeof(e1000_gg82563_cable_length_table) / \
89 sizeof(e1000_gg82563_cable_length_table[0]))
90
91/**
92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
93 * @hw: pointer to the HW structure
94 **/

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849/**
850 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
851 * @hw: pointer to the HW structure
852 *
853 * Perform a global reset to the ESB2 controller.
854 **/
855static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
856{
87#define GG82563_CABLE_LENGTH_TABLE_SIZE \
88 (sizeof(e1000_gg82563_cable_length_table) / \
89 sizeof(e1000_gg82563_cable_length_table[0]))
90
91/**
92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
93 * @hw: pointer to the HW structure
94 **/

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849/**
850 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
851 * @hw: pointer to the HW structure
852 *
853 * Perform a global reset to the ESB2 controller.
854 **/
855static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
856{
857 u32 ctrl, icr;
857 u32 ctrl;
858 s32 ret_val;
859
860 DEBUGFUNC("e1000_reset_hw_80003es2lan");
861
862 /*
863 * Prevent the PCI-E bus from sticking if there is no TLP connection
864 * on the last TLP read/write transaction when MAC is reset.
865 */

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885
886 ret_val = e1000_get_auto_rd_done_generic(hw);
887 if (ret_val)
888 /* We don't want to continue accessing MAC registers. */
889 goto out;
890
891 /* Clear any pending interrupt events. */
892 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
858 s32 ret_val;
859
860 DEBUGFUNC("e1000_reset_hw_80003es2lan");
861
862 /*
863 * Prevent the PCI-E bus from sticking if there is no TLP connection
864 * on the last TLP read/write transaction when MAC is reset.
865 */

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885
886 ret_val = e1000_get_auto_rd_done_generic(hw);
887 if (ret_val)
888 /* We don't want to continue accessing MAC registers. */
889 goto out;
890
891 /* Clear any pending interrupt events. */
892 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
893 icr = E1000_READ_REG(hw, E1000_ICR);
893 E1000_READ_REG(hw, E1000_ICR);
894
895 ret_val = e1000_check_alt_mac_addr_generic(hw);
896
897out:
898 return ret_val;
899}
900
901/**
902 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
903 * @hw: pointer to the HW structure
904 *
905 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
906 **/
907static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
908{
909 struct e1000_mac_info *mac = &hw->mac;
910 u32 reg_data;
911 s32 ret_val;
894
895 ret_val = e1000_check_alt_mac_addr_generic(hw);
896
897out:
898 return ret_val;
899}
900
901/**
902 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
903 * @hw: pointer to the HW structure
904 *
905 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
906 **/
907static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
908{
909 struct e1000_mac_info *mac = &hw->mac;
910 u32 reg_data;
911 s32 ret_val;
912 u16 kum_reg_data;
912 u16 i;
913
914 DEBUGFUNC("e1000_init_hw_80003es2lan");
915
916 e1000_initialize_hw_bits_80003es2lan(hw);
917
918 /* Initialize identification LED */
919 ret_val = mac->ops.id_led_init(hw);

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931 /* Zero out the Multicast HASH table */
932 DEBUGOUT("Zeroing the MTA\n");
933 for (i = 0; i < mac->mta_reg_count; i++)
934 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
935
936 /* Setup link and flow control */
937 ret_val = mac->ops.setup_link(hw);
938
913 u16 i;
914
915 DEBUGFUNC("e1000_init_hw_80003es2lan");
916
917 e1000_initialize_hw_bits_80003es2lan(hw);
918
919 /* Initialize identification LED */
920 ret_val = mac->ops.id_led_init(hw);

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932 /* Zero out the Multicast HASH table */
933 DEBUGOUT("Zeroing the MTA\n");
934 for (i = 0; i < mac->mta_reg_count; i++)
935 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
936
937 /* Setup link and flow control */
938 ret_val = mac->ops.setup_link(hw);
939
940 /* Disable IBIST slave mode (far-end loopback) */
941 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
942 &kum_reg_data);
943 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
944 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
945 kum_reg_data);
946
939 /* Set the transmit descriptor write-back policy */
940 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
941 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
942 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
943 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
944
945 /* ...for both queues. */
946 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));

--- 606 unchanged lines hidden --- 		947 /* Set the transmit descriptor write-back policy */
948 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
949 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
950 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
951 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
952
953 /* ...for both queues. */
954 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));

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