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ls1021a.dtsi (279385) ls1021a.dtsi (295436)
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *

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48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50
51/ {
52 compatible = "fsl,ls1021a";
53 interrupt-parent = <&gic>;
54
55 aliases {
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *

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48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50
51/ {
52 compatible = "fsl,ls1021a";
53 interrupt-parent = <&gic>;
54
55 aliases {
56 crypto = &crypto;
57 ethernet0 = &enet0;
58 ethernet1 = &enet1;
59 ethernet2 = &enet2;
56 serial0 = &lpuart0;
57 serial1 = &lpuart1;
58 serial2 = &lpuart2;
59 serial3 = &lpuart3;
60 serial4 = &lpuart4;
61 serial5 = &lpuart5;
62 sysclk = &sysclk;
63 };

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134 clock-frequency = <0>;
135 voltage-ranges = <1800 1800 3300 3300>;
136 sdhci,auto-cmd12;
137 big-endian;
138 bus-width = <4>;
139 status = "disabled";
140 };
141
60 serial0 = &lpuart0;
61 serial1 = &lpuart1;
62 serial2 = &lpuart2;
63 serial3 = &lpuart3;
64 serial4 = &lpuart4;
65 serial5 = &lpuart5;
66 sysclk = &sysclk;
67 };

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138 clock-frequency = <0>;
139 voltage-ranges = <1800 1800 3300 3300>;
140 sdhci,auto-cmd12;
141 big-endian;
142 bus-width = <4>;
143 status = "disabled";
144 };
145
146 sata: sata@3200000 {
147 compatible = "fsl,ls1021a-ahci";
148 reg = <0x0 0x3200000 0x0 0x10000>,
149 <0x0 0x20220520 0x0 0x4>;
150 reg-names = "ahci", "sata-ecc";
151 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&platform_clk 1>;
153 dma-coherent;
154 status = "disabled";
155 };
156
142 scfg: scfg@1570000 {
143 compatible = "fsl,ls1021a-scfg", "syscon";
144 reg = <0x0 0x1570000 0x0 0x10000>;
145 big-endian;
146 };
147
157 scfg: scfg@1570000 {
158 compatible = "fsl,ls1021a-scfg", "syscon";
159 reg = <0x0 0x1570000 0x0 0x10000>;
160 big-endian;
161 };
162
163 crypto: crypto@1700000 {
164 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
165 fsl,sec-era = <7>;
166 #address-cells = <1>;
167 #size-cells = <1>;
168 reg = <0x0 0x1700000 0x0 0x100000>;
169 ranges = <0x0 0x0 0x1700000 0x100000>;
170 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
171
172 sec_jr0: jr@10000 {
173 compatible = "fsl,sec-v5.0-job-ring",
174 "fsl,sec-v4.0-job-ring";
175 reg = <0x10000 0x10000>;
176 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
177 };
178
179 sec_jr1: jr@20000 {
180 compatible = "fsl,sec-v5.0-job-ring",
181 "fsl,sec-v4.0-job-ring";
182 reg = <0x20000 0x10000>;
183 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
184 };
185
186 sec_jr2: jr@30000 {
187 compatible = "fsl,sec-v5.0-job-ring",
188 "fsl,sec-v4.0-job-ring";
189 reg = <0x30000 0x10000>;
190 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
191 };
192
193 sec_jr3: jr@40000 {
194 compatible = "fsl,sec-v5.0-job-ring",
195 "fsl,sec-v4.0-job-ring";
196 reg = <0x40000 0x10000>;
197 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
198 };
199
200 };
201
148 clockgen: clocking@1ee1000 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 ranges = <0x0 0x0 0x1ee1000 0x10000>;
152
153 sysclk: sysclk {
154 compatible = "fixed-clock";
155 #clock-cells = <0>;

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179 reg = <0x0 0x10>;
180 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
181 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
182 clock-output-names = "cluster1-clk";
183 };
184 };
185
186 dspi0: dspi@2100000 {
202 clockgen: clocking@1ee1000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0x0 0x0 0x1ee1000 0x10000>;
206
207 sysclk: sysclk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;

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233 reg = <0x0 0x10>;
234 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
235 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
236 clock-output-names = "cluster1-clk";
237 };
238 };
239
240 dspi0: dspi@2100000 {
187 compatible = "fsl,vf610-dspi";
241 compatible = "fsl,ls1021a-v1.0-dspi";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 reg = <0x0 0x2100000 0x0 0x10000>;
191 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
192 clock-names = "dspi";
193 clocks = <&platform_clk 1>;
194 spi-num-chipselects = <5>;
195 big-endian;
196 status = "disabled";
197 };
198
199 dspi1: dspi@2110000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <0x0 0x2100000 0x0 0x10000>;
245 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
246 clock-names = "dspi";
247 clocks = <&platform_clk 1>;
248 spi-num-chipselects = <5>;
249 big-endian;
250 status = "disabled";
251 };
252
253 dspi1: dspi@2110000 {
200 compatible = "fsl,vf610-dspi";
254 compatible = "fsl,ls1021a-v1.0-dspi";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 reg = <0x0 0x2110000 0x0 0x10000>;
204 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
205 clock-names = "dspi";
206 clocks = <&platform_clk 1>;
207 spi-num-chipselects = <5>;
208 big-endian;

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337 reg = <0x0 0x2ad0000 0x0 0x10000>;
338 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&platform_clk 1>;
340 clock-names = "wdog-en";
341 big-endian;
342 };
343
344 sai1: sai@2b50000 {
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <0x0 0x2110000 0x0 0x10000>;
258 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
259 clock-names = "dspi";
260 clocks = <&platform_clk 1>;
261 spi-num-chipselects = <5>;
262 big-endian;

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391 reg = <0x0 0x2ad0000 0x0 0x10000>;
392 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&platform_clk 1>;
394 clock-names = "wdog-en";
395 big-endian;
396 };
397
398 sai1: sai@2b50000 {
399 #sound-dai-cells = <0>;
345 compatible = "fsl,vf610-sai";
346 reg = <0x0 0x2b50000 0x0 0x10000>;
347 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
400 compatible = "fsl,vf610-sai";
401 reg = <0x0 0x2b50000 0x0 0x10000>;
402 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&platform_clk 1>;
349 clock-names = "sai";
403 clocks = <&platform_clk 1>, <&platform_clk 1>,
404 <&platform_clk 1>, <&platform_clk 1>;
405 clock-names = "bus", "mclk1", "mclk2", "mclk3";
350 dma-names = "tx", "rx";
351 dmas = <&edma0 1 47>,
352 <&edma0 1 46>;
406 dma-names = "tx", "rx";
407 dmas = <&edma0 1 47>,
408 <&edma0 1 46>;
353 big-endian;
354 status = "disabled";
355 };
356
357 sai2: sai@2b60000 {
409 status = "disabled";
410 };
411
412 sai2: sai@2b60000 {
413 #sound-dai-cells = <0>;
358 compatible = "fsl,vf610-sai";
359 reg = <0x0 0x2b60000 0x0 0x10000>;
360 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
414 compatible = "fsl,vf610-sai";
415 reg = <0x0 0x2b60000 0x0 0x10000>;
416 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&platform_clk 1>;
362 clock-names = "sai";
417 clocks = <&platform_clk 1>, <&platform_clk 1>,
418 <&platform_clk 1>, <&platform_clk 1>;
419 clock-names = "bus", "mclk1", "mclk2", "mclk3";
363 dma-names = "tx", "rx";
364 dmas = <&edma0 1 45>,
365 <&edma0 1 44>;
420 dma-names = "tx", "rx";
421 dmas = <&edma0 1 45>,
422 <&edma0 1 44>;
366 big-endian;
367 status = "disabled";
368 };
369
370 edma0: edma@2c00000 {
371 #dma-cells = <2>;
372 compatible = "fsl,vf610-edma";
373 reg = <0x0 0x2c00000 0x0 0x10000>,
374 <0x0 0x2c10000 0x0 0x10000>,
375 <0x0 0x2c20000 0x0 0x10000>;
376 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-names = "edma-tx", "edma-err";
379 dma-channels = <32>;
380 big-endian;
381 clock-names = "dmamux0", "dmamux1";
382 clocks = <&platform_clk 1>,
383 <&platform_clk 1>;
384 };
385
423 status = "disabled";
424 };
425
426 edma0: edma@2c00000 {
427 #dma-cells = <2>;
428 compatible = "fsl,vf610-edma";
429 reg = <0x0 0x2c00000 0x0 0x10000>,
430 <0x0 0x2c10000 0x0 0x10000>,
431 <0x0 0x2c20000 0x0 0x10000>;
432 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
434 interrupt-names = "edma-tx", "edma-err";
435 dma-channels = <32>;
436 big-endian;
437 clock-names = "dmamux0", "dmamux1";
438 clocks = <&platform_clk 1>,
439 <&platform_clk 1>;
440 };
441
442 dcu: dcu@2ce0000 {
443 compatible = "fsl,ls1021a-dcu";
444 reg = <0x0 0x2ce0000 0x0 0x10000>;
445 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&platform_clk 0>;
447 clock-names = "dcu";
448 big-endian;
449 status = "disabled";
450 };
451
386 mdio0: mdio@2d24000 {
387 compatible = "gianfar";
388 device_type = "mdio";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0x0 0x2d24000 0x0 0x4000>;
392 };
393
452 mdio0: mdio@2d24000 {
453 compatible = "gianfar";
454 device_type = "mdio";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <0x0 0x2d24000 0x0 0x4000>;
458 };
459
460 enet0: ethernet@2d10000 {
461 compatible = "fsl,etsec2";
462 device_type = "network";
463 #address-cells = <2>;
464 #size-cells = <2>;
465 interrupt-parent = <&gic>;
466 model = "eTSEC";
467 fsl,magic-packet;
468 ranges;
469 dma-coherent;
470
471 queue-group@2d10000 {
472 #address-cells = <2>;
473 #size-cells = <2>;
474 reg = <0x0 0x2d10000 0x0 0x1000>;
475 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
478 };
479
480 queue-group@2d14000 {
481 #address-cells = <2>;
482 #size-cells = <2>;
483 reg = <0x0 0x2d14000 0x0 0x1000>;
484 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
487 };
488 };
489
490 enet1: ethernet@2d50000 {
491 compatible = "fsl,etsec2";
492 device_type = "network";
493 #address-cells = <2>;
494 #size-cells = <2>;
495 interrupt-parent = <&gic>;
496 model = "eTSEC";
497 ranges;
498 dma-coherent;
499
500 queue-group@2d50000 {
501 #address-cells = <2>;
502 #size-cells = <2>;
503 reg = <0x0 0x2d50000 0x0 0x1000>;
504 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
507 };
508
509 queue-group@2d54000 {
510 #address-cells = <2>;
511 #size-cells = <2>;
512 reg = <0x0 0x2d54000 0x0 0x1000>;
513 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
516 };
517 };
518
519 enet2: ethernet@2d90000 {
520 compatible = "fsl,etsec2";
521 device_type = "network";
522 #address-cells = <2>;
523 #size-cells = <2>;
524 interrupt-parent = <&gic>;
525 model = "eTSEC";
526 ranges;
527 dma-coherent;
528
529 queue-group@2d90000 {
530 #address-cells = <2>;
531 #size-cells = <2>;
532 reg = <0x0 0x2d90000 0x0 0x1000>;
533 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
536 };
537
538 queue-group@2d94000 {
539 #address-cells = <2>;
540 #size-cells = <2>;
541 reg = <0x0 0x2d94000 0x0 0x1000>;
542 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
545 };
546 };
547
394 usb@8600000 {
395 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
396 reg = <0x0 0x8600000 0x0 0x1000>;
397 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
398 dr_mode = "host";
399 phy_type = "ulpi";
400 };
401
402 usb3@3100000 {
403 compatible = "snps,dwc3";
404 reg = <0x0 0x3100000 0x0 0x10000>;
405 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
406 dr_mode = "host";
548 usb@8600000 {
549 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
550 reg = <0x0 0x8600000 0x0 0x1000>;
551 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
552 dr_mode = "host";
553 phy_type = "ulpi";
554 };
555
556 usb3@3100000 {
557 compatible = "snps,dwc3";
558 reg = <0x0 0x3100000 0x0 0x10000>;
559 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
560 dr_mode = "host";
561 snps,quirk-frame-length-adjustment = <0x20>;
407 };
408 };
409};
562 };
563 };
564};